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UM10360_0 

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 00.06 — 5 June 2009 

246 of 808

NXP Semiconductors

UM10360

Chapter 13: LPC17xx USB OTG controller

5.

Architecture

The architecture of the USB OTG controller is shown below in the block diagram.

The host, device, OTG, and I

2

C controllers can be programmed through the register 

interface. The OTG controller enables dynamic switching between host and device roles 
through the HNP protocol. One port may be connected to an external OTG transceiver to 
support an OTG connection. The communication between the register interface and an 
external OTG transceiver is handled through an I

2

C interface and through the external 

OTG transceiver interrupt signal.

For USB connections that use the device or host controller only (not OTG), the ports use 
an embedded USB Analog Transceiver (ATX).

 

6.

Modes of operation

The OTG controller is capable of operating in the following modes:

•

Host mode (see 

Figure 13–33

)

•

Device mode (see 

Figure 13–34

)

•

OTG mode (see 

Figure 13–35

)

7.

Pin configuration

The OTG controller has one USB port.

Fig 32. USB OTG controller block diagram

REGISTER

INTERFACE

BUS

MASTER

INTERFACE

USB

ATX

DMA interface

(AHB master)

register

interface

(AHB slave)

AHB b

us

I2C

CONTROLLER

DEVICE

CONTROLLER

HOST

CONTROLLER

EP_RAM

OTG

CONTROLLER

ATX

CONTROL

LOGIC/

PORT

MUX

USB

port

OTG

TRANSCEIVER

USB OTG BLOCK

Summary of Contents for LPC1751

Page 1: ...F T D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10360 LPC17xx User manual Rev 00 06 5 June 2009 User manual Document information Info Content Keywords LPC1768 LPC1766 LPC1765 LPC1764 LP...

Page 2: ...ation For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com NXP Semiconductors UM10360 LPC17xx user manual Revision history Rev D...

Page 3: ...timers 6 output general purpose PWM ultra low power RTC with separate battery supply and up to 70 general purpose I O pins 2 Features ARM Cortex M3 processor running at frequencies of up to 100 MHz A...

Page 4: ...tandard port pins Enhancements include multiple address recognition and monitor mode I2S Inter IC Sound interface for digital audio input or output with fractional rate control The I2S interface can b...

Page 5: ...sensitive interrupt sources Non maskable Interrupt NMI input Clock output function that can reflect the main oscillator clock IRC clock RTC clock CPU clock or the USB clock The Wakeup Interrupt Contro...

Page 6: ...07 1 LPC1766FBD100 LPC1765FBD100 LPC1764FBD100 LPC1758FBD80 LQFP80 plastic low profile quad flat package 80 leads body 12 12 1 4 mm SOT315 1 LPC1756FBD80 LPC1754FBD80 LPC1752FBD80 LPC1751FBD80 Table 2...

Page 7: ...main Multilayer AHB Matrix I2C2 I2S UARTs 2 3 SSP0 Real Time Clock 20 bytes of backup registers SSP1 UARTs 0 1 CAN 1 2 I2C 0 1 SPI0 Capture Compare Timers 0 1 Watchdog Timer PWM1 12 bit ADC Pin Connec...

Page 8: ...so that the CPU or DMA controller can write to APB devices without always waiting for APB write completion 7 ARM Cortex M3 processor The ARM Cortex M3 is a general purpose 32 bit microprocessor which...

Page 9: ...r pin or the 4 bit parallel trace port A Flash Patch and Breakpoint FPB is included The FPB can generate hardware breakpoints and remap specific addresses in code space to SRAM as a temporary method o...

Page 10: ...interface DMA controller Ethernet 10 100 MAC System bus D code bus I code bus DMAC regs USB regs Ethernet regs clock generation power control and other system functions SRAM 32 kB ROM 8 kB Flash 512 k...

Page 11: ...FFFF For devices with 256 kB of flash memory 0x0000 0000 0x0001 FFFF For devices with 128 kB of flash memory 0x0000 0000 0x0000 FFFF For devices with 64 kB of flash memory 0x0000 0000 0x0000 7FFF For...

Page 12: ...0x4000 0000 WDT TIMER0 TIMER1 UART0 UART1 reserved I2C0 SPI RTC backup registers GPIO interrupts pin connect SSP1 ADC CAN AF RAM CAN AF registers CAN common CAN1 CAN2 22 19 reserved I2C1 31 24 reserv...

Page 13: ...to occur at smaller boundaries An implication of this is that word and half word registers must be accessed all at once For example it is not possible to read or write the upper byte of a word regist...

Page 14: ...n The regions are areas of the memory map that are not implemented for a specific derivative These include all spaces marked reserved in Figure 2 3 For these areas both attempted data access and instr...

Page 15: ...ce are not defined in the LPC17xx documentation and are not a supported feature If software executes a write directly to the flash memory the flash accelerator will generate a Bus Fault exception Flas...

Page 16: ...on word address boundaries Details of the registers appear in the description of each function UM10360 Chapter 3 LPC17xx System control Rev 00 06 5 June 2009 User manual Table 6 Pin summary Pin name...

Page 17: ...al Reset is de asserted the oscillator is running a fixed number of clocks have passed and the flash controller has completed its initialization The reset logic is shown in the following block diagram...

Page 18: ...o access the Flash Accelerator will insert wait cycles until the flash is ready 2 The flash wake up timer 9 bit starts counting when the synchronized reset is de asserted The flash wakeup timer genera...

Page 19: ...2 6 V thresholds include some hysteresis In normal operation this hysteresis allows the 2 9 V detection to reliably interrupt or a regularly executed event loop to sense the condition Table 8 Reset S...

Page 20: ...on has four registers associated with it The EXTINT register contains the interrupt flags The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters 1 Reset Value reflects th...

Page 21: ...function though of course pins selected for other functions may cause interrupts from those functions Table 10 External Interrupt Flag register EXTINT address 0x400F C140 bit description Bit Symbol D...

Page 22: ...ions may cause interrupts from those functions Note Software should only change a bit in this register when its interrupt is disabled in the NVIC state readable in the ISERn ICERn registers and should...

Page 23: ...as a clock source Prior to starting the main oscillator a frequency range must be selected by configuring the OSCRANGE bit in the SCS register 2 EXTPOLAR2 0 EINT2 is low active or falling edge sensiti...

Page 24: ...Chapter 3 LPC17xx System control 6 OSCSTAT Main oscillator status RO 0 0 The main oscillator is not ready to be used as a clock source 1 The main oscillator is ready to be used as a clock source The...

Page 25: ...ction PLLs Clock dividers APB dividers Power control Wake up timer External clock output 2 Register description All registers regardless of size are on word address boundaries Details of the registers...

Page 26: ...not be used with the CAN1 2 block if the CAN baud rate is higher than 100 kbit s The nominal IRC frequency is 4 MHz Upon power up or any chip reset the LPC17xx uses the IRC as the clock source Softwa...

Page 27: ...Refer to Section 4 5 PLL0 Phase Locked Loop 0 for details The on board oscillator in the LPC17xx can operate in one of two modes slave mode and oscillation mode In slave mode the input clock signal s...

Page 28: ...clock sources may be chosen to drive PLL0 and ultimately the CPU and on chip peripheral devices The clock sources available are the main oscillator the RTC oscillator and the Internal RC oscillator T...

Page 29: ...the range of 32 kHZ to 50 MHz may initially be divided down by a value N which may be in the range of 1 to 256 This input division provides a greater number of possibilities in providing a wide range...

Page 30: ...ccomplished by a feed sequence similar to that of the Watchdog Timer Details are provided in the description of the PLL0FEED register PLL0 is turned off and bypassed following a chip Reset and by ente...

Page 31: ...iven see Section 4 5 8 PLL0 Feed register PLL0FEED 0x400F C08C PLL0CFG PLL0 Configuration Register Holding register for updating PLL0 configuration values Values written to this register do not take e...

Page 32: ...able When one and after a valid PLL0 feed this bit will activate PLL0 and allow it to lock to the requested frequency See PLL0STAT register Table 4 22 0 1 PLLC0 PLL0 Connect Setting PLLC0 to one after...

Page 33: ...4395 1 288 0307 4578 1 300 0238 4725 1 309 6576 4807 1 315 0316 5127 1 336 0031 5188 1 340 0008 5400 1 353 8944 5493 1 359 9892 5859 1 383 9754 6042 1 395 9685 6075 1 398 1312 6104 1 400 0317 6409 1...

Page 34: ...th values found in PLL0CON and PLL0CFG because changes to those registers do not take effect until a proper PLL0 feed has occurred see Section 4 5 8 PLL0 Feed register PLL0FEED 0x400F C08C 13672 2 448...

Page 35: ...s locked so if the interrupt is used the interrupt service routine must disable the PLOCK0 interrupt prior to exiting 5 7 PLL0 Modes The combinations of PLLE0 and PLLC0 are shown in Table 4 23 Table 2...

Page 36: ...L0 Wake up from Power down mode does not automatically restore PLL0 settings this must be done in software Typically a routine to activate PLL0 wait for lock and then connect PLL0 can be called at the...

Page 37: ...uencies specifically when the RTC is used to clock PLL0 a set of 65 additional M values have been selected for supporting baud rate generation CAN USB operation and attaining even MHz frequencies Thes...

Page 38: ...g in mind the requirement for USB support in 1 above and that lower values of FCCO result in lower power dissipation 3 Choose a value for the PLL input frequency FIN This can be a clock obtained from...

Page 39: ...Hz RTC clock source will be used as the system clock source Calculations M FCCO N 2 FIN The smallest frequency for FCCO that can produce our desired CPU clock rate and is within the PLL0 operating ran...

Page 40: ...ctive with one feed sequence The PLL0CFG can only be updated when PLL0 is disabled 6 Enable PLL0 with one feed sequence 7 Change the CPU Clock Divider setting for the operation with PLL0 It is critica...

Page 41: ...der value is 2 it is insured that the output of PLL1 has a 50 duty cycle A block diagram of PLL1 is shown in Figure 4 9 6 1 PLL1 register description PLL1 is controlled by the registers shown in Table...

Page 42: ...0F C0A0 The PLL1CON register contains the bits that enable and connect PLL1 Enabling PLL1 allows it to attempt to lock to the current settings of the multiplier and divider values Connecting PLL1 caus...

Page 43: ...n PLL1CON and PLL1CFG because changes to those registers do not take effect until a proper PLL1 feed has occurred see Section 4 6 6 PLL1 Feed register PLL1FEED 0x400F C0AC Table 29 PLL1 Control regist...

Page 44: ...scription Reset value 4 0 MSEL1 Read back for the PLL1 Multiplier value This is the value currently used by PLL1 0 6 5 PSEL1 Read back for the PLL1 Divider value This is the value currently used by PL...

Page 45: ...an be called at the beginning of any interrupt service routine that might be called due to the wake up It is important not to attempt to restart a PLL by simply feeding it when execution resumes after...

Page 46: ...r frequency FOSC USBCLK must be the whole non fractional multiple of FOSC meaning that the possible values for FOSC are 12 MHz 16 MHz and 24 MHz 3 Calculate the value of M to configure the MSEL1 bits...

Page 47: ...g CPU operation to a low rate for temporary power savings without turning off PLL0 Note when the USB interface is used in an application CCLK must be at least 18 MHz in order to support internal opera...

Page 48: ...eeded for USB specification compliance see Table 4 17 7 3 IRC Trim Register IRCTRIM 0x400F C1A4 This register is used to trim the on chip 4 MHz oscillator 7 4 Peripheral Clock Selection registers 0 an...

Page 49: ...C Peripheral clock selection for ADC 00 27 26 PCLK_CAN1 Peripheral clock selection for CAN1 00 29 28 PCLK_CAN2 Peripheral clock selection for CAN2 00 31 30 PCLK_ACF Peripheral clock selection for CAN...

Page 50: ...are selected by bits in the PCON register See Table 4 44 The same register contains flags that indicate whether entry into each reduced power mode actually occurred The LPC17xx also implements a sepa...

Page 51: ...atic The Deep Sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks Since all dynamic operation of the chi...

Page 52: ...egisters Entry to Deep Power down mode causes the DPDFLAG bit in PCON to be set see Table 4 44 To optimize power conservation the user has the additional option of turning off or retaining power to th...

Page 53: ...reduced power mode will be lost When 0 the Brown Out Detect function remains active during Power down and Deep Sleep modes See the System Control Block chapter for details of Brown Out detection 0 3...

Page 54: ...e USB Activity Interrupt generated by activity on the USB bus pins For the wake up process to take place the related function must be mapped to a pin and the corresponding interrupt must be enabled 8...

Page 55: ...bit 1 5 Reserved NA 6 PCPWM1 PWM1 power clock control bit 1 7 PCI2C0 The I2C0 interface power clock control bit 1 8 PCSPI The SPI interface power clock control bit 1 9 PCRTC The RTC power clock contro...

Page 56: ...z IRC oscillator as the clock source This allows chip operation to begin quickly If the main oscillator or one or both PLLs are needed by the application software will need to enable these features an...

Page 57: ...system clock that is related to one of the on chip clocks For most clock sources the division may be by 1 When the CPU clock is selected and is higher than approximately 50 MHz the output must be divi...

Page 58: ...0 Clock is divided by 3 1111 Clock is divided by 16 8 CLKOUT_EN CLKOUT enable control allows switching the CLKOUT source without glitches Clear to stop CLKOUT on the next falling edge Set to enable CL...

Page 59: ...control A flash memory interface Figure 5 12 shows a simplified diagram of the flash accelerator blocks and data paths In the following descriptions the term fetch applies to an explicit flash read re...

Page 60: ...ddress will cause a new fetch to be initiated after the flash operation has completed 3 Register description The flash accelerator is controlled by the register shown in Table 5 48 More detailed descr...

Page 61: ...the same time the multilayer matrix gives precedence to the data access This is because a stalled data access always slows down execution while a stalled instruction fetch often does not When the flas...

Page 62: ...ready in another buffer A prefetch in progress may be aborted by a data access in order to minimize CPU stalls A prefetched flash line is latched within the flash memory but the flash accelerator does...

Page 63: ...ection 34 4 2 for details of NVIC operation 3 Interrupt sources Table 6 50 lists the interrupt sources for each peripheral function Each peripheral device may have one or more interrupt lines to the V...

Page 64: ...dem Control Change End of Auto Baud ABEO Auto Baud Time Out ABTO 23 0x5C UART 2 Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI End of Au...

Page 65: ...0x98 ADC A D Converter end of conversion 39 0x9C BOD Brown Out detect 40 0xA0 USB USB_INT_REQ_LP USB_INT_REQ_HP USB_INT_REQ_DMA 41 0xA4 CAN CAN Common CAN 0 Tx CAN 0 Rx CAN 1 Tx CAN 1 Rx 42 0xA8 GPDMA...

Page 66: ...addition when pins are selected to be A to D converter inputs they are no longer 5V tolerant and must be limited to the voltage at the ADC positive reference pin VREFP UM10360 Chapter 7 LPC17xx Pin co...

Page 67: ...input digital section of the pad is disabled I RXD0 Receiver input for UART0 I AD0 6 A D converter 0 input 6 P0 4 I2SRX_CLK RD2 CAP2 0 81 I O P0 4 General purpose digital input output pin I O I2SRX_CL...

Page 68: ...open drain pin O MAT3 0 Match output for Timer 3 channel 0 P0 11 RXD2 SCL2 MAT3 1 49 40 I O P0 11 General purpose digital input output pin I RXD2 Receiver input for UART2 I O SCL2 I2C2 clock input ou...

Page 69: ...urpose digital input output pin When configured as an ADC input digital section of the pad is disabled I AD0 1 A D converter 0 input 1 I O I2SRX_WS Receive Word Select It is driven by the master and r...

Page 70: ...he USB specification revision 2 0 Full speed and Low speed mode only I O USB_D USB bidirectional D line P1 0 to P1 31 I O Port 1 Port 1 is a 32 bit I O port with individual direction controls for each...

Page 71: ...eneral purpose digital input output pin O MCABORT Motor control PWM active low fast abort O PWM1 3 Pulse Width Modulator 1 channel 3 output I O SSEL0 Slave Select for SSP0 P1 22 MCOB0 USB_PWRD MAT1 0...

Page 72: ...bus power Note This signal must be HIGH for USB reset to occur I AD0 4 A D converter 0 input 4 P1 31 SCK1 AD0 5 20 17 I O P1 31 General purpose digital input output pin When configured as an ADC input...

Page 73: ...figured to be an RS 485 EIA 485 output enable signal P2 8 TD2 TXD2 ENET_MDC 65 50 I O P2 8 General purpose digital input output pin O TD2 CAN2 transmitter output O TXD2 Transmitter output for UART2 O...

Page 74: ...not available P3 25 MAT0 0 PWM1 2 27 I O P3 25 General purpose digital input output pin O MAT0 0 Match output for Timer 0 channel 0 O PWM1 2 Pulse Width Modulator 1 output 2 P3 26 STCLK MAT0 1 PWM1 3...

Page 75: ...rence This should be the same voltage as VSS but should be isolated to minimize noise and error VDD 3V3 28 54 71 96 1 21 42 56 77 1 I 3 3 V supply voltage This is the power supply voltage for I O othe...

Page 76: ...function on a port pin excludes other peripheral functions available on the same pin However the GPIO input stays connected and may be read by software or used to contribute to the GPIO interrupt feat...

Page 77: ...ports This includes the use of the on chip pull up pull down resistor feature and a special open drain operating mode The on chip pull up pull down resistor can be selected for every port pin regardle...

Page 78: ...is in the normal not open drain mode 00 1 Pin is in the open drain mode Table 56 Pin Connect Block Register Map Name Description Access Reset Value 1 Address PINSEL0 Pin function select register 0 R...

Page 79: ...rol bit in the FIO0DIR register is effective only when the GPIO function is selected for a pin For other functions the direction is controlled automatically PINMODE_OD3 Open drain mode control registe...

Page 80: ...t 0 20 DTR1 Reserved SCL1 00 11 10 P0 21 1 GPIO Port 0 21 RI1 Reserved RD1 00 13 12 P0 22 GPIO Port 0 22 RTS1 Reserved TD1 00 15 14 P0 23 1 GPIO Port 0 23 AD0 0 I2SRX_CLK CAP3 0 00 17 16 P0 24 1 GPIO...

Page 81: ...Reserved Reserved 00 5 4 P1 18 GPIO Port 1 18 USB_UP_LED PWM1 1 CAP1 0 00 7 6 P1 19 GPIO Port 1 19 MC0A USB_PPWR CAP1 1 00 9 8 P1 20 GPIO Port 1 20 MCFB0 PWM1 2 SCK0 00 11 10 P1 21 1 GPIO Port 1 21 M...

Page 82: ...n For other functions direction is controlled automatically 5 8 Pin Function Select Register 10 PINSEL10 0x4002 C028 Only bit 3 of this register is used to control the Trace function on pins P2 2 thro...

Page 83: ...ace is enabled TPIU signals are available on the pins hosting them regardless of the PINSEL4 content 31 4 Reserved Software should not write 1 to these bits NA Table 65 Pin Mode select register 0 PINM...

Page 84: ...select register values Table 66 Pin Mode select register 1 PINMODE1 address 0x4002 C044 bit description PINMODE1 Symbol Description Reset value 1 0 P0 16MODE Port 1 pin 16 control see P0 00MODE 00 3...

Page 85: ...e P0 00MODE 00 17 16 P1 24MODE Port 1 pin 24 control see P0 00MODE 00 19 18 P1 25MODE Port 1 pin 25 control see P0 00MODE 00 21 20 P1 26MODE Port 1 pin 26 control see P0 00MODE 00 23 22 P1 27MODE 1 Po...

Page 86: ...iption Reset value 17 0 Reserved NA 19 18 P3 25MODE 1 Port 3 pin 25 control see P0 00MODE 00 21 20 P3 26MODE 1 Port 3 pin 26 control see P0 00MODE 00 31 22 Reserved NA Table 71 Pin Mode select registe...

Page 87: ...n 16 open drain mode control see P0 00OD 0 17 P0 17OD Port 0 pin 17 open drain mode control see P0 00OD 0 18 P0 18OD Port 0 pin 18 open drain mode control see P0 00OD 0 19 P0 19OD 3 Port 0 pin 19 open...

Page 88: ...en drain mode control see P1 00OD 0 21 P1 21OD 1 Port 1 pin 21 open drain mode control see P1 00OD 0 22 P1 22OD Port 1 pin 22 open drain mode control see P1 00OD 0 23 P1 23OD Port 1 pin 23 open drain...

Page 89: ...pen drain mode control see P2 00OD 0 8 P2 08OD Port 2 pin 8 open drain mode control see P2 00OD 0 9 P2 09OD Port 2 pin 9 open drain mode control see P2 00OD 0 10 P2 10OD Port 2 pin 10 open drain mode...

Page 90: ...in the normal not open drain mode 1 P4 28 pin is in the open drain mode 29 P4 28OD Port 4 pin 29 open drain mode control see P4 28OD 0 31 30 Reserved NA Table 76 Open Drain Pin Mode select register 4...

Page 91: ...registers are byte half word and word addressable Entire port value can be written in one instruction GPIO registers are accessible by the GPDMA Bit level set and clear registers allow a single instru...

Page 92: ...ments with the LPC2300 series ARM7 based products the LPC17xx implements portions of five 32 bit General Purpose I O ports Details on a specific GPIO port usage can be found in Section 8 3 The registe...

Page 93: ...value register using FIOMASK The current state of digital port pins can be read from this register regardless of pin direction or alternate function selection as long as pins are not configured as an...

Page 94: ...R register every fast GPIO port can also be controlled via several byte and half word accessible registers listed in Table 9 82 too Next to providing the same functions as the FIODIR register these ad...

Page 95: ...e FIOxDIR0 Fast GPIO Port x Direction control register 0 Bit 0 in FIOxDIR0 register corresponds to pin Px 0 bit 7 to pin Px 7 8 byte R W 0x00 FIO0DIR0 0x2009 C000 FIO1DIR0 0x2009 C020 FIO2DIR0 0x2009...

Page 96: ...0 Fast GPIO Port x output Set register 0 Bit 0 in FIOxSET0 register corresponds to pin Px 0 bit 7 to pin Px 7 8 byte R W 0x00 FIO0SET0 0x2009 C018 FIO1SET0 0x2009 C038 FIO2SET0 0x2009 C058 FIO3SET0 0x...

Page 97: ...hese additional registers allow easier and faster access to the physical port pins Table 85 Fast GPIO port output Clear register FIO0CLR to FIO7CLR addresses 0x2009 C01C to 0x2009 C09C bit description...

Page 98: ...affects the entire port Access to a port pin via the FIOxPIN register is conditioned by the corresponding bit of the FIOxMASK register see Section 9 5 5 Only pins masked with zeros in the Mask registe...

Page 99: ...ption Generic Register name Description Register length bits access Reset value PORTn Register Address Name FIOxPIN0 Fast GPIO Port x Pin value register 0 Bit 0 in FIOxPIN0 register corresponds to pin...

Page 100: ...ic Register name Description Register length bits access Reset value PORTn Register Address Name FIOxMASK0 Fast GPIO Port x Mask register 0 Bit 0 in FIOxMASK0 register corresponds to pin Px 0 bit 7 to...

Page 101: ...g interrupts on Port 0 1 There is at least one pending interrupt on Port 0 1 Reserved The value read from a reserved bit is not defined NA 2 P2Int Port 2 GPIO interrupt pending 0 0 There are no pendin...

Page 102: ...r P0 25 0 26 P0 26ER Enable rising edge interrupt for P0 26 0 27 P0 27ER 1 Enable rising edge interrupt for P0 27 0 28 P0 28ER 1 Enable rising edge interrupt for P0 28 0 29 P0 29ER Enable rising edge...

Page 103: ...is enabled on P0 0 1 P0 1EF Enable falling edge interrupt for P0 1 0 2 P0 2EF Enable falling edge interrupt for P0 2 0 3 P0 3EF Enable falling edge interrupt for P0 3 0 4 P0 4EF 1 Enable falling edge...

Page 104: ...rupt for P0 30 0 31 Reserved NA Table 94 GPIO Interrupt Enable for port 0 Falling Edge IO0IntEnF address 0x4002 8094 bit description Bit Symbol Value Description Reset value Table 95 GPIO Interrupt En...

Page 105: ...of Rising Edge Interrupt for P0 5 0 6 P0 6REI Status of Rising Edge Interrupt for P0 6 0 7 P0 7REI Status of Rising Edge Interrupt for P0 7 0 8 P0 8REI Status of Rising Edge Interrupt for P0 8 0 9 P0...

Page 106: ...of Rising Edge Interrupt for P2 6 0 7 P2 7REI Status of Rising Edge Interrupt for P2 7 0 8 P2 8REI Status of Rising Edge Interrupt for P2 8 0 9 P2 9REI Status of Rising Edge Interrupt for P2 9 0 10 P...

Page 107: ...24 0 25 P0 25FEI Status of Falling Edge Interrupt for P0 25 0 26 P0 26FEI Status of Falling Edge Interrupt for P0 26 0 27 P0 27FEI 1 Status of Falling Edge Interrupt for P0 27 0 28 P0 28FEI 1 Status o...

Page 108: ...0 0 Corresponding bits in IOxIntStatR and IOxIntStatF are unchanged 1 Corresponding bits in IOxIntStatR and IOxStatF are cleared 1 P0 1CI Clear GPIO port Interrupts for P0 1 0 2 P0 2CI Clear GPIO port...

Page 109: ...0 30CI Clear GPIO port Interrupts for P0 30 0 31 Reserved NA Table 100 GPIO Interrupt Clear register for port 0 IO0IntClr 0x4002 808C bit description Bit Symbol Value Description Reset value Table 101...

Page 110: ...put pin s to both high and low levels at the same time When FIOSET or FIOCLR are used only pin bit s written with 1 will be changed while those written as 0 will remain unaffected Writing to the FIOPI...

Page 111: ...uite of control registers half or full duplex operation flow control control frames hardware acceleration for transmit retry receive packet filtering and wake up on LAN activity Automatic frame transm...

Page 112: ...ic optimized by buffering and prefetching Enhanced Ethernet features Receive filtering Multicast and broadcast frame support for both transmit and receive Optional automatic FCS insertion CRC for tran...

Page 113: ...t Interface Management MIIM interface 4 Architecture and operation Figure 10 15 shows the internal architecture of the Ethernet block The block diagram for the Ethernet block consists of The host regi...

Page 114: ...rame or a much smaller amount of data Each descriptor contains a pointer to a memory buffer that holds data associated with a fragment the size of the fragment buffer and details of how the fragment w...

Page 115: ...to know which descriptors if any are available for their use including whether the descriptor array is empty or full Similarly driver software must set up pointers to data that will be transmitted by...

Page 116: ...e fields should be done by using the scatter gather functionality of the Ethernet core to avoid unnecessary copying of data The hardware adds the preamble and start frame delimiter fields and can opti...

Page 117: ...ia the AHB interface through the serial management connection of the MIIM bus typically operating at 2 5 MHz 8 2 Example PHY Devices Some examples of compatible PHY devices are shown in Table 10 103 9...

Page 118: ...lling DMA transfers flow control and filtering Reading from reserved addresses or reserved bits leads to unpredictable data Writing to reserved addresses or reserved bits has no effect Reading of writ...

Page 119: ...ister 0x5000 0130 to 0x5000 0154 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined TSV0 0x5000 0158 RO Transmit status vector 0 register T...

Page 120: ...Down 0x5000 0FF4 R W Power down register 0x5000 0FF8 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 106 Register definitions Symb...

Page 121: ...e transmitted and received 0 3 DELAYED CRC This bit determines the number of bytes if any of proprietary header information that exist on the front of IEEE 802 3 frames When 1 four bytes of header ign...

Page 122: ...he Standard When disabled the MAC will abort when the excessive deferral limit is reached 0 31 15 Reserved User software should not write ones to reserved bits The value read from a reserved bit is no...

Page 123: ...er IPGR1 the MAC continues timing IPGR2 and transmits knowingly causing a collision thus ensuring fair access to medium Its range of values is 0x0 to IPGR2 The recommended value is 0xC 12d 0x0 31 15 R...

Page 124: ...000 bit description Bit Symbol Function Reset value 0 SHORTCUT PAUSE QUANTA This bit reduces the effective PAUSE quanta from 64 byte times to 1 byte time 0 1 TEST PAUSE This bit causes the MAC Control...

Page 125: ...0x5000 0020 bit description Bit Symbol Function Reset value Table 117 Clock select encoding Clock Select Bit 5 Bit 4 Bit 3 Bit 2 Maximum AHB clock supported Host Clock divided by 4 0 0 0 x 10 Host Clo...

Page 126: ...0028 bit description Bit Symbol Function Reset value 4 0 REGISTER ADDRESS This field represents the 5 bit Register Address field of Mgmt cycles Up to 32 registers can be accessed 0x0 7 5 Unused 0x0 1...

Page 127: ...x5000 0040 The bit definition of this register is shown in Table 10 123 The station address is used for perfect address filtering and for sending pause control frames For the ordering of the octets in...

Page 128: ...tion is shown in Table 10 126 Table 124 Station Address register SA1 address 0x5000 0044 bit description Bit Symbol Function Reset value 7 0 STATION ADDRESS 4th octet This field holds the fourth octet...

Page 129: ...t of the Rx TxEnable bit in the Command register and the channel has committed the status and data of the current frame to memory The status also transitions to inactive if the transmit queue is empty...

Page 130: ...n Table 10 130 The receive number of descriptors register defines the number of descriptors in the descriptor array for which RxDescriptor is the base address The number of descriptors should match th...

Page 131: ...sumeIndex After a frame has been processed by software software should increment the RxConsumeIndex The value must be wrapped to 0 once the value of RxDescriptorNumber has been reached If the RxProduc...

Page 132: ...smit Produce Index Register TxProduceIndex 0x5000 0128 The Transmit Produce Index register TxProduceIndex has an address of 0x5000 0128 Its bit definition is shown in Table 10 136 The transmit produce...

Page 133: ...smit status vector registers store the most recent transmit status returned by the MAC Since the status vector consists of more than 4 bytes status is distributed over two registers TSV0 and TSV1 Thes...

Page 134: ...and should typically only be read when the transmit and receive processes are halted Table 10 139 lists the bit definitions of the TSV1 register 7 Excessive Defer Packet was deferred in excess of 607...

Page 135: ...tor register RSV address 0x5000 0160 bit description Bit Symbol Function Reset value 15 0 Received byte count Indicates length of received frame 0x0 16 Packet previously ignored Indicates that a packe...

Page 136: ...l duplex mode the MirrorCounter specifies the number of cycles before re issuing the Pause control frame 0x0 31 16 PauseTimer In full duplex mode the PauseTimer specifies the value that is inserted in...

Page 137: ...ould not write ones to reserved bits The value read from a reserved bit is not defined NA 12 MagicPacketEnWoL When set to 1 the result of the magic packet filter will generate a WoL interrupt when the...

Page 138: ...gister Details of Hash filter table use can be found in Section 10 17 10 Receive filtering on page 168 Table 145 Receive Filter WoL Clear register RxFilterWoLClear address 0x5000 0208 bit description...

Page 139: ...error in the receive queue The fatal interrupt should be resolved by a Rx soft reset The bit is not set when there is a nonfatal overrun error 0 1 RxErrorInt Interrupt trigger on receive errors Align...

Page 140: ...been processed while the Interrupt bit in the Control field of the descriptor was set 0 4 TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor underrun situations 0 5 TxError...

Page 141: ...0x5000 0FF4 The bit definition of the register is listed in Table 10 152 Setting the bit will return an error on all read and write accesses on the MACAHB interface except for accesses to the Power Do...

Page 142: ...ster using a minus one encoding style e g if the array has 8 elements the register value should be 7 Parallel to the descriptors there is an array of statuses For each element of the descriptor array...

Page 143: ...f the control word bits is listed in Table 10 154 Table 10 155 lists the fields in the receive status elements from the status array Each receive status consists of two words The StatusHashCRC word co...

Page 144: ...LAN Indicates a VLAN frame 20 FailFilter Indicates this frame has failed the Rx filter These frames will not normally pass to memory But due to the limitation of the size of the buffer part of this fr...

Page 145: ...ze Error Overrun and NoDescriptor bits 15 2 Transmit descriptors and statuses Figure 10 18 depicts the layout of the transmit descriptors in memory Transmit descriptors are stored in an array in memor...

Page 146: ...ddress value containing the base address of the data buffer The definition of the control word bits is listed in Table 10 159 Table 10 160 shows the one field transmit status Table 158 Transmit descri...

Page 147: ...ock will be initialized Software initialization of the Ethernet block should include initialization of the descriptor and status arrays as well as the receiver fragment buffers To transmit a packet th...

Page 148: ...The Ethernet block generates errors for several conditions The AHB interface will return a read error when there is an AHB read access to a write only register likewise a write error is returned when...

Page 149: ...ion on the AHB bus gives priority to the DMA hardware in the case of simultaneous requests A descriptor is owned either by the device driver or by the Ethernet hardware Only the owner of a descriptor...

Page 150: ...ray element is kept empty to be able to easily distinguish the full or empty state by looking at the value of the produce index and consume index An array must have at least 2 elements to be able to i...

Page 151: ...t registers MAC1 MAC2 etc in the MAC Enable the receive and transmit data paths Depending on the PHY the software needs to initialize registers in the PHY via the MII Management interface The software...

Page 152: ...by setting the TxEnable bit in the Command register Before enabling the data paths several options can be programmed in the MAC such as automatic flow control transmit to receive loop back for verific...

Page 153: ...frames from the descriptor array the TxStatus bit in the Status register will return to 1 active Tx DMA manager reads the Tx descriptor array When the TxEnable bit is set the Tx DMA manager reads the...

Page 154: ...er than the last fragment the error flags are returned via the AHB interface If the Ethernet block detects a transmission error during transmission of a multi fragment frame all remaining fragments of...

Page 155: ...ftware layers re send the frame In the third case the hardware is in an undefined state and needs to be soft reset by setting the TxReset bit in the Command register After reporting a LateCollision Ex...

Page 156: ...will allocate the descriptor and status array in memory In this example an array of four descriptors is allocated the array is 4x2x4 bytes and aligned on a 4 byte address boundary Since the number of...

Page 157: ...scriptor in the array describes the initial 8 bytes of the payload the third descriptor in the array describes the remaining 4 bytes of the frame In the third descriptor the Last bit in the Control wo...

Page 158: ...ng an underrun error which is why descriptors and data read commands are issued as soon as possible and pipelined Using an RMII PHY the data communication between the Ethernet block and the PHY is com...

Page 159: ...he Status word The value of the RxProduceIndex is only updated after the fragment data and the fragment status information has been committed to memory which is checked by an internal tag protocol in...

Page 160: ...gister is set if there is an AlignmentError RangeError LengthError SymbolError CRCError or NoDescriptor error nonfatal overrun errors are reported in the RxError bit of the IntStatus register fatal Ov...

Page 161: ...ovide descriptors for the initial fragments but did not provide the descriptors for the rest of the fragments or if a nonfatal data Overrun occurred the hardware will set the RxErrorInt bit of the Int...

Page 162: ...h fragment buffer can be between 1 byte and 2 k bytes The base address of the fragment buffer is stored in the Packet field of the descriptors The number of bytes in the fragment buffer is stored in t...

Page 163: ...stributed over three fragment buffers After writing the initial 8 bytes in the first fragment buffer the status for the first fragment buffer will be written and the Rx DMA will continue filling the s...

Page 164: ...e discarded The Ethernet block will set the Error and LateCollision bits in the frame s status fields The TxError bit in the IntStatus register will be set If the corresponding bit in the IntEnable re...

Page 165: ...OL bit in the MAC1 configuration register If the RX FLOW CONTROL bit is zero then the Ethernet block ignores received pause control frames When a pause frame is received on the Rx side of the Ethernet...

Page 166: ...unting the pause timer the pause can be extended as long as TxFlowControl is asserted This continues until TxFlowControl is de asserted when a final pause frame having a pause timer value of 0x0000 is...

Page 167: ...generated to stall receive packets by sending continuous preamble that basically jams any other transmissions on the Ethernet medium When the Ethernet block operates in half duplex mode asserting the...

Page 168: ...the device driver software using up bandwidth memory space and host CPU time Address filtering can be implemented using the perfect address filter or the imperfect hash filter The latter produces a 6...

Page 169: ...ss match When a frame with a unicast destination address is received a perfect filter compares the destination address with the 6 byte station address programmed in the station address registers SA0 S...

Page 170: ...me imperfect hash filter that is available for multicast addresses can also be used for unicast addresses This is useful to be able to respond to a multitude of unicast addresses without enabling all...

Page 171: ...own the power management software should clear the register by writing the RxFilterWolClear register NOTE when entering in power down mode a receive frame might be not entirely stored into the Rx buff...

Page 172: ...icPacketWoL bit is set in the RxFilterWoLStatus register Software can reset the bit writing a 1 to the corresponding bit of the RxFilterWoLClear register Example An example of a Magic Packet with stat...

Page 173: ...with its status before returning to the INACTIVE state Also if the Receive descriptor array is full the state machine will return to the INACTIVE state For the state machine in Figure 10 23 a soft res...

Page 174: ...r 64 bytes for VLAN frames the Ethernet block can pad the frame to 64 or 68 bytes including a 4 bytes CRC Frame Check Sequence FCS Padding is affected by the value of the AUTO DETECT PAD ENABLE ADPEN...

Page 175: ...d byte count in the RSV register may be invalid because the frame may exceed the maximum size the RxSize fields from the receive status arrays will be valid Frame lengths are checked by comparing the...

Page 176: ...logic and the receive function in the MAC The value after a hardware reset assertion is 0 RESET Rx Setting this bit will reset the receive function in the MAC The value after a hardware reset asserti...

Page 177: ...t the TxReset bit in the Command register this bit clears automatically Reset the RESET MCS Tx bit in the MAC1 register to 0 To reset just the receive data path the device driver software has to Disab...

Page 178: ...would include inter packet gaps in both the transmit and receive channels that reduce the bandwidth requirements over a larger time frame Types of DMA access and their bandwidth requirements The inte...

Page 179: ...ransmitted and received data This gives 7 16 of the data rate which 5 4688 Mbps This gives a total rate of 36 Mbps for the traffic generated by the Ethernet DMA function 18 3 Overall bandwidth Overall...

Page 180: ...t byte int crc CRC result int q0 q1 q2 q3 temporary variables crc 0xFFFFFFFF for i 0 i frame_len i byte frame_no_fcs for j 0 j 2 j if crc 28 byte 3 0x00000001 q3 0x04C11DB7 else q3 0x00000000 if crc 2...

Page 181: ...0_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 181 of 808 NXP Semiconductors UM10360 Chapter 10 LPC17xx Ethernet For obtaining the destination and source address hash CRCs this...

Page 182: ...ing the appropriate Interrupt Set Enable register 6 Initialization see Section 11 13 3 Introduction The Universal Serial Bus USB is a four wire bus that supports communication between a host and one o...

Page 183: ...amic switching between CPU controlled and DMA modes Double buffer implementation for Bulk and Isochronous endpoints 5 Fixed endpoint configuration Table 11 163 shows the supported endpoint configurati...

Page 184: ...pt In 1 to 64 No 2 4 Bulk Out 8 16 32 64 Yes 2 5 Bulk In 8 16 32 64 Yes 3 6 Isochronous Out 1 to 1023 Yes 3 7 Isochronous In 1 to 1023 Yes 4 8 Interrupt Out 1 to 64 No 4 9 Interrupt In 1 to 64 No 5 10...

Page 185: ...tion parallel serial conversion bit stuffing de stuffing CRC checking generation PID verification generation address recognition and handshake evaluation generation 6 3 Endpoint RAM EP_RAM Each endpoi...

Page 186: ...ECT signal should control an external switch that connects the 1 5 kOhm resistor between D and 3 3V Software can then control the CONNECT signal by writing to the CON bit using the SIE Set Device Stat...

Page 187: ...cription of this mode 8 Pin description 9 Clocking and power management This section describes the clocking and power management features of the USB Device Controller 9 1 Power requirements The USB pr...

Page 188: ...that DMA throughput is not affected by turning off the AHB master clock 2 ms after the last DMA access the AHB master clock is automatically disabled to help conserve power If desired software also h...

Page 189: ...Device interrupt registers USBIntSt USB Interrupt Status R W 0x8000 0000 0x400F C1C0 USBDevIntSt USB Device Interrupt Status RO 0x0000 0010 0x5000 C200 USBDevIntEn USB Device Interrupt Enable R W 0x00...

Page 190: ...he contents of this register USBClkCtrl is a read write register DMA registers USBDMARSt USB DMA Request Status RO 0x0000 0000 0x5000 C250 USBDMARClr USB DMA Request Clear WO 2 0x0000 0000 0x5000 C254...

Page 191: ...er also contains the USB_NEED_CLK status and EN_USB_INTS control bits USBIntSt is a read write register Table 167 USBClkCtrl register USBClkCtrl address 0x5000 CFF4 bit description Bit Symbol Descript...

Page 192: ...red A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power down mode see Section 4 8 8 Wake up from Reduced Power Mo...

Page 193: ...KT The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register USBTxPLen 0 8 EP_RLZED Endpoints realized Set when Realize Endpoint...

Page 194: ...29 28 27 26 25 24 Symbol Bit 23 22 21 20 19 18 17 16 Symbol Bit 15 14 13 12 11 10 9 8 Symbol ERR_INT EP_RLZED Bit 7 6 5 4 3 2 1 0 Symbol TxENDPKT Rx ENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRA...

Page 195: ...n error All non isochronous IN endpoints generate an interrupt when a packet is successfully transmitted or when a NAK handshake is sent on the bus and the interrupt on NAK feature is enabled see Sect...

Page 196: ...3 Isochronous endpoint NA 7 EP3TX Endpoint 3 Isochronous endpoint NA 8 EP4RX Endpoint 4 Data Received Interrupt bit 0 9 EP4TX Endpoint 4 Data Transmitted Interrupt bit or sent a NAK 0 10 EP5RX Endpoi...

Page 197: ...Select Endpoint Clear Interrupt command can be directly invoked using the SIE command registers but using USBEpIntClr is recommended because of its ease of use Each physical endpoint has its own reser...

Page 198: ...SB_INT_REQ_HP or USB_INT_REQ_LP interrupt line USBEpIntPri is a write only register Bit 15 14 13 12 11 10 9 8 Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX Bit 7 6 5 4 3 2 1 0 Symbol EP3TX EP...

Page 199: ...nce the RAM depth has to be adjusted to the next word boundary Also each buffer has one word header showing the size of the packet length received The EP_ RAM space in words required for the physical...

Page 200: ...responding bits in USBReEp To calculate the required EP_RAM space for the realized endpoints see Section 11 10 4 1 Realization of endpoints is a multi cycle operation Pseudo code for endpoint realizat...

Page 201: ...register is addressed through the USBEpIn register The USBEpIn register will hold the physical endpoint number Writing to USBMaxPSize will set the array element pointed to by USBEpIn USBEpIn is a writ...

Page 202: ...cted endpoint buffer is fetched The data is in little endian format the first byte received from the USB bus will be available in the least significant byte of USBRxData USBRxData is a read only regis...

Page 203: ...int buffer before starting this process For data buffers larger than the endpoint s MaxPacketSize software should submit data in packets of MaxPacketSize and send the remaining extra bytes in the last...

Page 204: ...register Table 196 USB Transmit Packet Length register USBTxPLen address 0x5000 C224 bit description Bit Symbol Value Description Reset value 9 0 PKT_LNGTH The remaining number of bytes to be written...

Page 205: ...data transfer if the DMA is enabled for the corresponding endpoint in the USBEpDMASt register The DMA cannot be enabled for control endpoints EP0 and EP1 USBDMARSt is a read only register Table 198 U...

Page 206: ...in the USBDMARSt register Writing zero has no effect This register allows software to raise a DMA request This can be useful when switching from Slave to DMA mode of operation for an endpoint if a pa...

Page 207: ...MA transfer for an endpoint can start only if the corresponding bit is set in this register USBEpDMASt is a read only register Table 203 USB DMA Request Set register USBDMARSet address 0x5000 C258 bit...

Page 208: ...rror condition is detected during a DMA transfer the corresponding bit is cleared by hardware USBEpDMADis is a write only register 10 7 8 USB DMA Interrupt Status register USBDMAIntSt 0x5000 C290 Each...

Page 209: ...DMAIntSt address 0x5000 C290 bit description Bit Symbol Value Description Reset value 0 EOT End of Transfer Interrupt bit 0 0 All bits in the USBEoTIntSt register are 0 1 At least one bit in the USBEo...

Page 210: ...ster Table 210 USB End of Transfer Interrupt Status register USBEoTIntSt address 0x5000 C2A0s bit description Bit Symbol Value Description Reset value 31 0 EPxx Endpoint xx 2 xx 31 End of Transfer Int...

Page 211: ...g bit is set in this register USBSysErrIntSt is a read only register 10 7 17 USB System Error Interrupt Clear register USBSysErrIntClr 0x5000 C2BC Writing one to a bit in this register clears the corr...

Page 212: ...e mode If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the USBEpIntEn register the corresponding status bit in the USBEpIntSt is set For non isochronous endpoints...

Page 213: ...er The USB interrupts are routed to the NVIC only if EN_USB_INTS is set DMA mode If an interrupt event occurs on a non control endpoint and the endpoint interrupt is not enabled in the USBEpIntEn regi...

Page 214: ...UM10360 Chapter 11 LPC17xx USB device controller For simplicity USBDevIntEn and USBDMAIntEn are not shown Fig 27 Interrupt event handling USB_INT_REQ_HP USB_INT_REQ_LP USB_INT_REQ_DMA EN_USB_INTS to...

Page 215: ...MD_PHASE field set to the value 0x02 Read and the CMD_CODE field set with command code the read corresponds to On completion of the read the CDFULL bit of USBDevInSt will be set indicating the data is...

Page 216: ...command code table Command name Recipient Code Hex Data phase Device commands Set Address Device D0 Write 1 byte Configure Device Device D8 Write 1 byte Set Mode Device F3 Write 1 byte Read Current Fr...

Page 217: ...K is functional the 48 MHz clock can be stopped when the device enters suspend state 1 USB_NEED_CLK is fixed to 1 the 48 MHz clock cannot be stopped when the device enters suspend state 1 INAK_CI Inte...

Page 218: ...et Device Status Command 0xFE Data write 1 byte The Set Device Status command sets bits in the Device Status Register Table 223 Set Device Status Register bit description Bit Symbol Value Description...

Page 219: ...code 3 SUS_CH Suspend SUS bit change indicator The SUS bit can toggle because The device goes into the suspended state The device is disconnected The device receives resume signalling on its upstream...

Page 220: ...ing Error 0010 Unknown PID 0011 Unexpected Packet any packet sequence violation from the specification 0100 Error in Token CRC 0101 Error in Data CRC 0110 Time Out Error 0111 Babble 1000 Error in End...

Page 221: ...f the B_1_FULL and B_2_FULL bits For single buffered endpoints this bit simply reflects the status of B_1_FULL 0 0 For an IN endpoint at least one write endpoint buffer is empty 1 For an OUT endpoint...

Page 222: ...hysical endpoint number in hex Not all bits can be set for all types of endpoints 6 B_2_FULL The buffer 2 status 0 0 Buffer 2 is empty 1 Buffer 2 is full 7 Reserved user software should not write ones...

Page 223: ...nt Clear Interrupt command read the new SETUP data and again check the status of the PO bit See Section 11 14 Slave mode operation for a description of when this command is used 12 14 Validate Buffer...

Page 224: ...um cclk frequency is 18 MHz For the procedure for determining the PLL setting and configuration see Section 4 5 11 Procedure for determining PLL0 settings 3 Enable the device controller clocks by sett...

Page 225: ...rupt generation In slave mode data packet transfer between RAM and an endpoint buffer can be initiated in response to an endpoint interrupt Endpoint interrupts are enabled using the USBEpIntEn registe...

Page 226: ...will be sent in the next frame If the software clears WR_EN before the entire packet is written writing will start again from the beginning the next time WR_EN is set for this endpoint Both RD_EN and...

Page 227: ...128 byte boundary of RAM that is accessible to both the CPU and DMA controller Figure 11 28 illustrates the UDCA and its relationship to the UDCA Head USBUDCAH register and DMA Descriptors 15 3 Trigg...

Page 228: ...RAM at word aligned addresses DDs for non isochronous endpoints are four words long DDs for isochronous endpoints are five words long The parameters associated with a DMA transfer are The start addre...

Page 229: ...tches the new descriptor when it is finished with the current one 15 4 4 Isochronous_endpoint When set this bit indicates that the descriptor belongs to an isochronous endpoint Hence 5 words have to b...

Page 230: ...s field The following codes are defined NotServiced No packet has been transferred yet BeingServiced At least one packet is transferred NormalCompletion The DD is retired because the end of the buffer...

Page 231: ...ets This is applicable only for OUT endpoints Offset 0 indicates that the message length starts from the first byte of the first packet 15 4 15 Isochronous_packetsize_memory_address The memory buffer...

Page 232: ...For OUT endpoints the current packet is read from the EP_RAM by the DMA Engine and transferred to on chip RAM memory locations starting from DMA_buffer_start_addr For IN endpoints the data is fetched...

Page 233: ...ne by setting both the Max_packet_size and DMA_buffer_length fields in the DD to 0 On processing a No_Packet DD the DMA engine clears the DMA request bit in USBDMARSt corresponding to the endpoint wit...

Page 234: ...length field of the isochronous packet size word is used For each frame an isochronous data packet of size specified by this field is transferred from the USB device to the host and Isochronous_packet...

Page 235: ...up this concatenated transfer back into the original delta transfers and transfer them to separate DMA buffers This is achieved by setting the DMA mode to Auto Transfer Length Extraction ATLE mode in...

Page 236: ...he USB transfer specified by Message_length_position from the incoming data packets and writes it in the DMA_buffer_length field of the DD To ensure that both bytes of the DMA_buffer_length are extrac...

Page 237: ...DD are sent as a short packet on USB which marks the end of the USB transfer for the host If the last buffer length completes on a MaxPacketSize packet boundary the device software must program the n...

Page 238: ...er length is 0 an empty packet will be sent to indicate the end of the USB transfer 16 Double buffered endpoint operation The Bulk and Isochronous endpoints of the USB Device Controller are double buf...

Page 239: ...o occur The active buffer is now B_2 The next data packet sent by the host will be placed in B_2 The following example illustrates how double buffering works for a Bulk IN endpoint in Slave mode Assum...

Page 240: ...y manually starting a packet transfer using the USBDMARSet register 16 2 Isochronous endpoints For isochronous endpoints the active data buffer is switched by hardware when the FRAME interrupt occurs...

Page 241: ...Interrupts Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register 6 Initialization see Section 13 11 3 Introduction This section describes the host portion of the USB...

Page 242: ...ces resume signaling on the bus The Host Controller has four USB states visible to the SW Driver HCCA register points to Interrupt and Isochronous Descriptors List ControlHeadED and BulkHeadED registe...

Page 243: ...data USB Connector USB_D I O Negative differential data USB Connector USB_UP_LED O GoodLink LED control signal Control USB_PPWR O Port power enable Host power switch USB_PWRD I Port power status Host...

Page 244: ...ime interval in a frame and the full speed maximum packet size which would not cause an overrun 0x2EDF HcFmRemaining 0x5000 C038 R A 14 bit counter showing the bit time remaining in the current frame...

Page 245: ...n 13 10 2 and Section 4 8 8 5 Interrupts Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register 6 Initialization see Section 13 11 3 Introduction This chapter describes...

Page 246: ...rnal OTG transceiver to support an OTG connection The communication between the register interface and an external OTG transceiver is handled through an I2C interface and through the external OTG tran...

Page 247: ...eiver For OTG functionality an external OTG transceiver must be connected to the LPC17xx Use the internal USB transceiver for USB signalling and use the external OTG transceiver for OTG functionality...

Page 248: ...The USB port is connected as device There is no OTG functionality on the USB port 8 Register description The OTG and I2C registers are summarized in the following table The Device and Host registers...

Page 249: ...ar OTGStCtrl 0x5000 C110 R W OTG Status and Control OTGTmr 0x5000 C114 R W OTG Timer I2C registers I2C_RX 0x5000 C300 RO I2C Receive I2C_TX 0x5000 C300 WO I2C Transmit I2C_STS 0x5000 C304 RO I2C Statu...

Page 250: ...of OTGIntSet is the same as in OTGIntSt 8 5 OTG Interrupt Clear Register OTGIntClr 0x5000 C10C Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt register Writing...

Page 251: ...it is set and the timer value is reloaded into the counter The timer is not disabled in this mode Table 237 OTG Status Control register OTGStCtrl address 0x5000 C110 bit description Bit Symbol Descrip...

Page 252: ...s bit when HNP_SUCCESS or HNP_FAILURE is set 0 15 11 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 31 16 TMR_CNT Current timer coun...

Page 253: ...t I2C_CTL bit 7 Reading an empty FIFO gives unpredictable data results 4 AHB_CLK_EN AHB master clock enable 0 0 Disable the AHB clock 1 Enable the AHB clock 31 5 NA Reserved user software should not w...

Page 254: ...locks as well as the current state of the external buses Individual bits are enabled as interrupts by the I2C_CTL register and routed to the I2C_USB_INT bit in USBIntSt Table 241 I2C Receive register...

Page 255: ...Once a transmission is started the transmitter must have data to transmit as long as it isn t followed by a STOP condition or it will hold SCL low until more data is available The Slave Data Request b...

Page 256: ...Done Interrupt Enable This enables the TDI interrupt signalling that this I2C issued a STOP condition 0 0 Disable the TDI interrupt 1 Enable the TDI interrupt 1 AFIE Transmitter Arbitration Failure In...

Page 257: ...can be written to the transmit FIFO Note that this is not full It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register...

Page 258: ...TG stack provides the communication to the host and device controllers 9 HNP support This section describes the hardware support for the Host Negotiation Protocol HNP provided by the OTG controller Wh...

Page 259: ...ication USB OTG supplement version 1 2 USB 2 0 specification ISP1302 data sheet and user manual 9 1 B device peripheral to host switching In this case the default role of the OTG controller is periphe...

Page 260: ...Device states is also shown B device states are in bold font with a circle around them Fig 38 Hardware support for B device switching from peripheral state to host state idle set HNP_SUCCESS set PORT_...

Page 261: ...be polled but this is not necessary if the corresponding interrupt is enabled Following are code examples that show how the actions in Figure 13 39 are accomplished The examples assume that ISP1302 i...

Page 262: ...DI to be set while OTG_I2C_STS TDI Clear TDI OTG_I2C_STS TDI 9 2 A device host to peripheral HNP switching In this case the role of the OTG controller is host A device and the A device switches roles...

Page 263: ...rdware actions setting TMR HNP_SUCCESS and HNP_FAILURE The relationship of the software actions to the Dual Role A Device states is also shown A device states are shown in bold font with a circle arou...

Page 264: ...be polled but this is not necessary if the corresponding interrupt is enabled Following are code examples that show how the actions in Figure 13 41 are accomplished The examples assume that ISP1302 is...

Page 265: ...ear BDIS_ACON_EN in external OTG transceiver Set BDIS_ACON_EN in ISP1302 OTG_I2C_TX 0x15A Send ISP1302 address R W 0 OTG_I2C_TX 0x005 Send Mode Control 1 Clear register address OTG_I2C_TX 0x210 Clear...

Page 266: ...s is done will be somewhat more involved HC_RH_PORT_STAT1 PSS 10 Clocking and power management The OTG controller clocking is shown in Figure 13 42 A clock switch controls each clock with the exceptio...

Page 267: ...s detected on the USB bus The dev_need_clk signal is de asserted if a disconnect is detected CON bit is cleared in the SIE Get Device Status register Section 11 10 6 This signal allows DEV_CLK_EN to b...

Page 268: ...that DMA throughput is not affected by any latency associated with re enabling ahb_master_clk 2 ms after the last DMA access host_dma_need_clk is de asserted to help conserve power This signal allows...

Page 269: ...reserved User manual Rev 00 06 5 June 2009 269 of 808 NXP Semiconductors UM10360 Chapter 13 LPC17xx USB OTG controller 4 Enable the desired USB pin functions by writing to the corresponding PINSEL reg...

Page 270: ...56 to enable FIFO 5 Pins Select UART pins through the PINSEL registers and pin modes through the PINMODE registers Section 8 5 Remark UART receive pins should not have pull down resistors enabled 6 In...

Page 271: ...R A F T D R A F T D R A F T D R A UM10360_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 271 of 808 NXP Semiconductors UM10360 Chapter 14 LPC17xx UART0 2 3 4 Register descriptio...

Page 272: ...dual interrupt enable bits for the 7 potential UART interrupts R W 0x00 U0IER 0x4000 C004 U2IER 0x4009 8004 U3IER 0x4009 C004 IIR Interrupt ID Register Identifies which interrupt s are pending RO 0x01...

Page 273: ...n be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in UnLCR must be zero in order to access the UnTHR The UnTHR is always Write Only 4 3...

Page 274: ...Tn Divisor Latch MSB Register along with the U0DLL register determines the baud rate of the UARTn 0x00 Table 253 UARTn Interrupt Enable Register U0IER address 0x4000 C004 U2IER 0x4009 8004 U3IER 0x400...

Page 275: ...Interrupt Service Routine The UARTn RLS interrupt UnIIR 3 1 011 is the highest priority interrupt and is set whenever any one of four error conditions occur on the UARTn Rx input overrun error OE pari...

Page 276: ...ee Section 14 4 8 UARTn Line Status Register U0LSR 0x4000 C014 U2LSR 0x4009 8014 U3LSR 0x4009 C014 Read Only 3 For details see Section 14 14 4 1 UARTn Receiver Buffer Register U0RBR 0x4000 C000 U2RBR...

Page 277: ...e enabled via the FIFO Enable bit in the FCR register Table 256 UARTn FIFO Control Register U0FCR address 0x4000 C008 U2FCR 0x4009 8008 U3FCR 0x4007 C008 Write Only bit description Bit Symbol Value De...

Page 278: ...transmitted or received 4 8 UARTn Line Status Register U0LSR 0x4000 C014 U2LSR 0x4009 8014 U3LSR 0x4009 C014 Read Only The UnLSR is a read only register that provides status information on the UARTn T...

Page 279: ...ity error is associated with the character at the top of the UARTn RBR FIFO 0 0 Parity error status is inactive 1 Parity error status is active 3 Framing Error FE When the stop bit of a received chara...

Page 280: ...contain valid data 1 0 UnTHR and or the UnTSR contains valid data 1 UnTHR and the UnTSR are empty 7 Error in RX FIFO RXFE UnLSR 7 is set when a character with a Rx error such as framing error parity...

Page 281: ...next falling edge of the UARTn Rx pin The auto baud function can generate two interrupts The UnIIR ABTOInt interrupt will get set if the interrupt is enabled UnIER ABToIntEn is set and the auto baud...

Page 282: ...art bit setting the baud rate measurement counter is reset and the UARTn UnRSR is reset The UnRSR baud rate is switch to the highest rate 2 A falling edge on UARTn Rx pin triggers the beginning of the...

Page 283: ...Register enables and configures the IrDA mode on each UART The value of UnICR should not be changed while transmitting or receiving data or data loss or corruption may occur a Mode 0 start bit and LSB...

Page 284: ...re scaler takes the APB clock and generates an output clock according to the specified fractional requirements Important If the fractional divider is active DIVADDVAL 0 and DLM 0 the value of the DLL...

Page 285: ...3FDR register value does not comply to these two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be divide...

Page 286: ...06 5 June 2009 286 of 808 NXP Semiconductors UM10360 Chapter 14 LPC17xx UART0 2 3 Fig 44 Algorithm for setting UART dividers PCLK BR Calculating UART baudrate BR DL est PCLK 16 x BR DLest is an integ...

Page 287: ...DLM 0 DLL 4 DIVADDVAL 5 and MULVAL 8 According to Equation 14 2 the UART rate is 115384 This rate has a relative error of 0 16 from the originally specified 115200 4 13 UARTn Transmit Enable Register...

Page 288: ...TX Holding Register FIFO UnTHR The UARTn TX Shift Register UnTSR reads the data stored in the UnTHR and assembles the data to transmit via the serial output pin TXDn Table 265 UARTn Transmit Enable Re...

Page 289: ...erator block UnBRG generates the timing enables used by the UARTn TX block The UnBRG clock input source is the APB clock PCLK The main clock is divided down per the divisor specified in the UnDLL and...

Page 290: ...2009 All rights reserved User manual Rev 00 06 5 June 2009 290 of 808 NXP Semiconductors UM10360 Chapter 14 LPC17xx UART0 2 3 Fig 45 UART0 2 and 3 block diagram APB INTERFACE UnLCR UnRX DDIS UnLSR UnF...

Page 291: ...RT pins through PINSEL registers and pin modes through the PINMODE registers Section 8 5 Remark UART receive pins should not have pull down resistors enabled 6 Interrupts To enable UART interrupts set...

Page 292: ...on is stored in U1MSR3 and is a source for a priority level 4 interrupt if enabled U1IER 3 1 DSR1 Input Data Set Ready Active low signal indicates if the external modem is ready to establish a communi...

Page 293: ...rupt Enable Register Contains individual interrupt enable bits for the 7 potential UART1 interrupts R W 0x00 0x4001 0004 when DLAB 0 U1IIR Interrupt ID Register Identifies which interrupt s are pendin...

Page 294: ...LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in U1LCR must be zero in order to access the U1THR The U1THR is always Write Only 4 3 UART1 Divisor Latch LSB and MSB Registe...

Page 295: ...r along with the U1DLL register determines the baud rate of the UART1 0x00 Table 273 UART1 Interrupt Enable Register U1IER address 0x4001 0004 when DLAB 0 bit description Bit Symbol Value Description...

Page 296: ...ill generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the U1IER 3 bit in the U1IER register In auto cts mode a transition on the CTS1 bit will trigger an interrupt o...

Page 297: ...R 3 1 110 The RDA is activated when the UART1 Rx FIFO reaches the trigger level defined in U1FCR7 6 and is reset when the UART1 Rx FIFO depth falls below the trigger level When the RDA interrupt goes...

Page 298: ...THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start up The initialization conditions implement a one character delay minus the stop bit whenever TH...

Page 299: ...acter timeout occurs See the description of the RX Trigger Level above The receiver DMA request is cleared by the DMA controller Table 276 UART1 FIFO Control Register U1FCR address 0x4001 0008 Write O...

Page 300: ...r length 10 7 bit character length 11 8 bit character length 2 Stop Bit Select 0 1 stop bit 0 1 2 stop bits 1 5 if U1LCR 1 0 00 3 Parity Enable 0 Disable parity generation and checking 0 1 Enable pari...

Page 301: ...he sending UART to continue transmitting data If Auto RTS mode is disabled the RTSen bit controls the RTS1 output of the UART1 If Auto RTS mode is enabled hardware controls the RTS1 output and the act...

Page 302: ...he last stop bit that is currently being sent In Auto CTS mode a change of the CTS1 signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set Delta CTS bit in the U1M...

Page 303: ...bits0 7 start bits0 7 stop start bits0 7 stop UART1 TX CTS1 pin stop Table 280 UART1 Line Status Register U1LSR address 0x4001 0014 Read Only bit description Bit Symbol Value Description Reset Value 0...

Page 304: ...rror status is active 4 Break Interrupt BI When RXD1 is held in the spacing state all zeroes for one full character transmission start data parity stop a break interrupt occurs Once the break conditio...

Page 305: ...hange of input CTS Cleared on an U1MSR read 0 0 No change detected on modem input CTS 1 State change detected on modem input CTS 1 Delta DSR Set upon state change of input DSR Cleared on an U1MSR read...

Page 306: ...edge of the least significant bit In mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of the UART1 Rx pin the length of the start bit Table 283 Auto baud Contr...

Page 307: ...asurement Also when auto baud is used any write to U1DLM and U1DLL registers should be done before U1ACR register write The minimum and the maximum baud rates supported by UART1 are function of pclk n...

Page 308: ...ining bits of the A a character 4 16 UART1 Fractional Divider Register U1FDR 0x4001 0028 The UART1 Fractional Divider Register U1FDR controls the clock pre scaler for the baud rate generation and can...

Page 309: ...R register value does not comply to these two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be divided 4...

Page 310: ...00 06 5 June 2009 310 of 808 NXP Semiconductors UM10360 Chapter 15 LPC17xx UART1 Fig 49 Algorithm for setting UART dividers PCLK BR Calculating UART baudrate BR DL est PCLK 16 x BR DLest is an integer...

Page 311: ...8 According to Equation 15 4 the UART rate is 115384 This rate has a relative error of 0 16 from the originally specified 115200 4 17 UART1 Transmit Enable Register U1TER 0x4001 0030 In addition to be...

Page 312: ...it is after a Reset data written to the THR is output on the TXD pin as soon as any preceding data has been sent If this bit cleared to 0 while a character is being sent the transmission of that chara...

Page 313: ...arity bit is set to 0 Each UART slave receiver can be assigned a unique address The slave can be programmed to either manually or automatically reject data following an address which is not theirs 5 O...

Page 314: ...parity 1 to the 8 bit value programmed into the RS485ADRMATCH register If the receiver is DISABLED RS485CTRL bit 1 1 any received byte will be discarded if it is either a data byte OR an address byte...

Page 315: ...a communications link between the CPU or host and the UART1 The UART1 receiver block U1RX monitors the serial input line RXD1 for valid input The UART1 RX Shift Register U1RSR accepts valid characters...

Page 316: ...ters U1IER and U1IIR The interrupt interface receives several one clock wide enables from the U1TX and U1RX blocks Status information from the U1TX and U1RX is stored in the U1LSR Control information...

Page 317: ...er initialization see CANMOD register Section 16 7 1 2 CAN controllers Controller Area Network CAN is the definition of a high performance communication protocol for serial data communication The CAN...

Page 318: ...no re transmission Listen Only Mode no acknowledge no active error flags Reception of own messages Self Reception Request 3 3 Acceptance filter features Fast hardware implemented search algorithm supp...

Page 319: ...face Management Logic interprets commands from the CPU controls internal addressing of the CAN Registers and provides interrupts and status information to the CPU 5 3 Transmit Buffers TXB The TXB repr...

Page 320: ...de represents the real transmitted Data Length Code which may be greater than 8 depending on transmitting CAN node Nevertheless the maximum number of received data bytes is 8 This should be taken into...

Page 321: ...ator drifts and to define the sample point and the number of samples to be taken within a bit time 5 7 Bit Stream Processor BSP The Bit Stream Processor is a sequencer controlling the data stream betw...

Page 322: ...bus Initiating a Global Self Test is similar to a normal CAN transmission In this case the transmission of a CAN message s is initiated by setting Self Reception Request bit SRR in conjunction with th...

Page 323: ...4003 C004 SFF_GRP_sa Standard Frame Group Start Address Register R W 0 0x4003 C008 EFF_sa Extended Frame Start Address Register R W 0 0x4003 C00C EFF_GRP_sa Extended Frame Group Start Address Register...

Page 324: ...4004 8038 TDB1 Transmit data bytes 5 8 Tx Buffer 1 R W CAN1TDB1 0x4004 403C CAN2TDB1 0x4004 803C TFI2 Transmit frame info Tx Buffer 2 R W CAN1TFI2 0x4004 4040 CAN2TFI2 0x4004 8040 TID2 Transmit Identi...

Page 325: ...ontroller register summary Generic Name Operating Mode Reset Mode Read Write Read Write Table 296 CAN Wake and Sleep registers Name Description Access Reset Value Address CANSLEEPCLR Allows clearing t...

Page 326: ...terrupt is generated A sleeping CAN Controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits Bus Free sequence Note that se...

Page 327: ...release the receive buffer 1 released The information in the Receive Buffer consisting of CANxRFS CANxRID and if applicable the CANxRDA and CANxRDB registers is released and becomes eligible for repl...

Page 328: ...cycles before a new interrupt is generated 5 This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit As long as the Data Overrun Status bit is set no fur...

Page 329: ...EWL 0x4004 4018 CAN2EWL 0x4004 8018 6 Mode bit 1 present and an Error Warning Interrupt is generated if enabled Afterwards the Transmit Error Counter is set to 127 and the Receive Error Counter is cle...

Page 330: ...ives information about the status of the Bus Off recovery If Bus Off is active a write access to TXERR in the range of 0 to 254 clears the Bus Off Flag and the controller will wait for one occurrence...

Page 331: ...the RBS bit in CANxSR and the RIE bit in CANxIER are both 1 indicating that a new message was received and stored in the Receive Buffer 0 0 1 TI1 0 reset 1 set Transmit Interrupt 1 This bit is set whe...

Page 332: ...set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register 0 0 9 TI2 0 reset 1 set Transmit Interrupt 2 This bit is set when the TBS2 bit in CANxSR goe...

Page 333: ...ID5 01110 ID4 ID0 01100 RTR Bit 01101 Reserved Bit 1 01001 Reserved Bit 0 01011 Data Length Code 01010 Data Field 01000 CRC Sequence 11000 CRC Delimiter 11001 Acknowledge Slot 11011 Acknowledge Delim...

Page 334: ...ration lost the corresponding arbitration lost interrupt is forced if enabled At that time the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register T...

Page 335: ...ble If the Error or Bus Status change see Status Register the CAN Controller requests the respective interrupt 0 X 3 DOIE Data Overrun Interrupt Enable If the Data Overrun Status bit is set see Status...

Page 336: ...cles per bit period and the location of the sample point 7 Table 302 CAN Bus Timing Register CAN1BTR address 0x4004 4014 CAN2BTR address 0x4004 8014 bit description Bit Symbol Value Function Reset Val...

Page 337: ...ach of the 3 Tx Buffers tTSEG1 tSCL TSEG1 1 tTSEG2 tSCL TSEG2 1 Table 303 CAN Error Warning Limit register CAN1EWL address 0x4004 4018 CAN2EWL address 0x4004 8018 bit description Bit Symbol Function R...

Page 338: ...x Buffer 2 has been successfully completed 12 RS Receive Status This bit is identical to the RS bit in the GSR 1 0 13 TS2 Transmit Status 2 1 0 0 idle There is no transmission from Tx Buffer 2 1 trans...

Page 339: ...8020 bit description Bit Symbol Function Reset Value RM Set 9 0 ID Index If the BP bit below is 0 this value is the zero based number of the Lookup Table RAM entry at which the Acceptance Filter match...

Page 340: ...address 7 11 CAN Receive Data register A CAN1RDA 0x4004 4028 CAN2RDA 0x4004 8028 This register contains the first 1 4 Data bytes of the current received message It is read only in normal operation but...

Page 341: ...Field where the first word of the Descriptor Field includes the TX Frame Info that describes the Frame Format the Data Length and whether it is a Remote or Data Frame In addition a TX Priority regist...

Page 342: ...ecified correctly to avoid bus errors if two CAN Controllers start a Remote Frame transmission with the same identifier simultaneously For reasons of compatibility no DLC 8 should be used If a value g...

Page 343: ...first 1 4 data bytes of the next transmit message The Data Length Code defines the number of transferred data bytes The first bit transmitted is the most significant bit of TX Data Byte 1 Table 311 CA...

Page 344: ...ep feature Table 314 CAN Transmit Data register B CAN1TDB 1 2 3 address 0x4004 40 3C 4C 5C CAN2TDB 1 2 3 address 0x4004 80 3C 4C 5C bit description Bit Symbol Function Reset Value RM Set 7 0 Data 5 If...

Page 345: ...255 to the Tx Error Counter forces the CAN Controller to Bus Off state If Bus Off BS in CANxSR is 1 writing any value 0 through 254 to the Tx Error Counter clears Bus Off When software clears RM in CA...

Page 346: ...uests Receive Transmit and other status The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers Each Receive and Transmit interrupt request from each controller is assign...

Page 347: ...sions have been completed successfully by the CAN1 controller same as TCS in CAN1GSR 1 17 16 TCS2 When 1 all requested transmissions have been completed successfully by the CAN2 controller same as TCS...

Page 348: ...able can be accessed only to disable or enable Messages Table 319 Central Miscellaneous Status Register CANMSR address 0x4004 0008 bit description Bit Symbol Description Reset Value 0 E1 When 1 one or...

Page 349: ...the Receive Interrupt RI In this mode all CAN message are accepted and stored in the Receive Buffers of active CAN Controllers 11 3 Acceptance filter Operating mode The Acceptance Filter is in Operati...

Page 350: ...cal order one per halfword two per word Since each CAN bus has its own address map each entry also contains the number of the CAN Controller 001 010 to which it applies The table of Standard Identifie...

Page 351: ...addresses Standard address ranges Extended Individual addresses and Extended address ranges These tables must be consecutive in memory The start of each of the latter four tables is implicitly the end...

Page 352: ...essages can be enabled by setting the eFCAN bit in the acceptance filter mode register 14 2 Section configuration registers The 10 bit section configuration registers are used for the ID look up table...

Page 353: ...ite the same value in this register and the SFF_GRP_sa register described below For compatibility with possible future devices write zeroes in bits 31 11 and 1 0 of this register If the eFCAN bit in t...

Page 354: ...e table is empty write the same value in this register and the EFF_GRP_sa register described below The largest value that should be written to this register is 0x800 when both Extended Tables are empt...

Page 355: ...t defined NA 11 2 EndofTable 1 The address above the last active address in the last active AF table For compatibility with possible future devices please write zeroes in bits 31 12 and 1 0 of this re...

Page 356: ...RAM It is cleared when software reads the LUTerrAd register This condition is ORed with the other CAN interrupts from the CAN controllers to produce the request that is connected to the NVIC 0 31 1 Re...

Page 357: ...CAN Controller 15 1 Acceptance filter search algorithm The identifier screening process of the acceptance filter starts in the following order 1 FullCAN Standard Frame Format Identifier Section 2 Exp...

Page 358: ...licit Identifier section if enabled The rest of the defined identifiers of this group 0x5B to 0x5F will find a match in this Group Identifier Section This way the user can switch dynamically between d...

Page 359: ...t be greater than or equal to the number of IDs for which automatic receive storage is to be done times two SFF_sa must be rounded up to a multiple of 4 if necessary The EndOfTable register must be le...

Page 360: ...a byte into the message object the Acceptance Filter will update the semaphore bits by setting SEM 1 0 11 Before reading a message object the CPU should read SEM 1 0 to determine the current state of...

Page 361: ...9 All rights reserved User manual Rev 00 06 5 June 2009 361 of 808 NXP Semiconductors UM10360 Chapter 16 LPC17xx CAN1 2 Fig 60 Semaphore procedure for reading an auto stored message read 1st word SEM...

Page 362: ...et the FullCAN Receive Interrupt is passed to the Vectored Interrupt Controller Application Software has to solve the following 1 Index Object number calculation based on the bit position in the FCANI...

Page 363: ...Source Channel SCC of the received FullCAN message is added to Message Object Fig 61 FullCAN section example of the ID look up table 0 FullCAN Explicit Standard Frame Format Identifier Section 11 bit...

Page 364: ...f an accepted FullCAN message and when the FullCAN Interrupt of the same object is asserted already During the first write access from the data storage of a FullCAN message object the Message Lost bit...

Page 365: ...a third message gets stored 3rd Object write Since the FullCAN Interrupt of that Object IntPndx is already asserted the Message Lost Signal gets asserted Fig 63 Normal case no messages lost 01 11 Int...

Page 366: ...ct another new message gets stored by the message handler In this case the FullCAN Interrupt bit gets set for a second time with the 2nd Object write 16 3 4 Scenario 3 1 Message gets overwritten indic...

Page 367: ...ritten indicated by Message Lost This scenario is a sub case to Scenario 3 in which the lost message is indicated by Message Lost Fig 66 Message overwritten indicated by semaphore bits and message los...

Page 368: ...essage object 2nd Object write The subsequent read out of that object by Software 1st Object read clears the pending Interrupt The 3rd Object write clears the Message Lost bit Every write ID SEM clear...

Page 369: ...RP_sa AND SFF_GRP_sa EFF_sa AND EFF_sa EFF_GRP_sa AND EFF_GRP_sa ENDofTable In cases of a section not being used the start address has to be set onto the value of the next section start address 17 3 E...

Page 370: ...egisters contain the values shown in the third column below In this case each table contains the decimal number of words and entries shown in the next two columns and the ID Index field of the CANRFS...

Page 371: ...iled example of acceptance filter tables and ID index values SFF_sa 000 d 000 h 0 0000 0000 b explicit SFF table lower_boundary 3 4 upper_boundary lower_boundary 3 lower_boundary 3 5 upper_boundary 6...

Page 372: ...e disabled and not used by the acceptance filter by setting the message disable bit in the upper and lower boundary identifier To provide memory space for four Groups of Standard Frame Format identifi...

Page 373: ...CC 8 0 SCC 6 0 SCC 0 SCC 1 Explicit Standard Frame Format Identifier Section Group of Standard Frame Format Identifier Section SFF_GRP_sa 0x10 SFF_sa 0x00 2 0 SCC 3 0 SCC Disabled 7 8 0 SCC Disabled 9...

Page 374: ...pace for eight FullCAN Explicit Standard Frame Format identifiers the SFF_sa register value is set to 0x10 The identifier with the Index 1 of this section is not used and therefore disabled Explicit s...

Page 375: ...re reported which were passed through the acceptance filtering process The following general rules for programming the Look up Table apply Fig 71 ID Look up table configuration example FullCAN activat...

Page 376: ...f 808 NXP Semiconductors UM10360 Chapter 16 LPC17xx CAN1 2 Each section has to be organized as a sorted list or table with an increasing order of the Source CAN Channel SCC in conjunction with the CAN...

Page 377: ...configure the pins SSEL MISO and MOSI respectively 4 Interrupts The SPI interrupt flag is enabled using the S0SPINT 0 bit Section 17 7 7 The SPI interrupt flag must be enabled in the NVIC see Table 6...

Page 378: ...synchronize the transfer of data across the SPI interface The SPI is always driven by the master and received by the slave The clock is programmable to be active high or active low The SPI is only act...

Page 379: ...when the SSEL signal goes active and ends when SSEL goes inactive When a device is a slave and CPHA is set to 1 the transfer starts on the first clock edge when the slave is selected and ends on the l...

Page 380: ...egister A write to the data register goes directly into the internal shift register Therefore data should only be written to this register when a transmit is not currently in progress Read data is buf...

Page 381: ...efore starting the transfer 2 Write the data to transmitted to the SPI Data Register optional Note that this can only be done when a slave SPI transfer is not in progress 3 Wait for the SPIF bit in th...

Page 382: ...EL signal goes inactive before the transfer is complete In the event of a slave abort the transmit and receive data for the transfer that was in progress are lost and the slave abort ABRT bit in the S...

Page 383: ...d ends with activation and deactivation of the SSEL signal 1 Data is sampled on the second clock edge of the SCK A transfer starts with the first clock edge and ends with the last sampling edge when t...

Page 384: ...ibed in Section 4 7 4 Table 342 SPI Status Register S0SPSR address 0x4002 0004 bit description Bit Symbol Description Reset Value 2 0 Reserved user software should not write ones to reserved bits The...

Page 385: ...s register will not start the sequence of events required to clear these status bits A write to this register will set an interrupt if the write data for the respective bit is a 1 7 7 SPI Interrupt Re...

Page 386: ...on Reset Value 0 SPIF SPI interrupt flag Set by the SPI interface to generate an interrupt Cleared by writing a 1 to this bit Note this bit will be set once when SPIE 1 and at least one of SPIF and WC...

Page 387: ...s to be configured SSP0CR0 and SSP0CR1 for SSP0 SSP1CR0 and SSP1CR1 for SSP1 See Section 18 6 1 and Section 18 6 2 6 DMA The Rx and Tx FIFOs of the SSP interfaces can be connected to the GPDMA control...

Page 388: ...e Select When the SSPn interface is a bus master it drives this signal to an active state before the start of serial data and then releases it to an inactive state after the serial data has been sent...

Page 389: ...th the SSP and the off chip serial slave device then clock each data bit into their serial shifter on the falling edge of each CLK The received data is transferred from the serial shifter to the recei...

Page 390: ...s for SPI format with CPOL 0 CPHA 0 are shown in Figure 18 75 In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance...

Page 391: ...CPHA 1 The transfer signal sequence for SPI format with CPOL 0 CPHA 1 is shown in Figure 18 76 which covers both single and continuous transfers In this configuration during idle periods The CLK signa...

Page 392: ...ans that data is captured on the falling edges and be propagated on the rising edges of the SCK signal In the case of a single word transmission after all bits of the data word are transferred the SSE...

Page 393: ...master and slave data are enabled onto their respective transmission lines At the same time the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagated...

Page 394: ...ic and the MSB of the 8 bit control frame to be shifted out onto the SO pin CS remains LOW for the duration of the frame transmission The SI pin remains tristated during this transmission The off chip...

Page 395: ...ta is to be sampled by the SSP slave CS must have a setup of at least two times the period of SK on which the SSP operates With respect to the SK rising edge previous to this edge CS must have a hold...

Page 396: ...x4003 0014 RIS Raw Interrupt Status Register R W SSP0RIS 0x4008 8018 SSP1RIS 0x4003 0018 MIS Masked Interrupt Status Register R W 0 SSP0MIS 0x4008 801C SSP1MIS 0x4003 001C ICR SSPICR Interrupt Clear R...

Page 397: ...away from the inter frame state of the clock line 1 SSP controller captures serial data on the second clock transition of the frame that is the transition back to the inter frame state of the clock li...

Page 398: ...4 SSP1CR1 0x4003 0004 bit description Bit Symbol Value Description Reset Value Table 352 SSPn Data Register SSP0DR address 0x4008 8008 SSP1DR 0x4003 0008 bit description Bit Symbol Description Reset V...

Page 399: ...even numbers only 6 6 SSPn Interrupt Mask Set Clear Register SSP0IMSC 0x4008 8014 SSP1IMSC 0x4003 0014 This register controls whether each of the four possible interrupt conditions in the SSP controll...

Page 400: ...IFO is full and another frame is completely received The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 0 1 RTIM Software should set this bit to e...

Page 401: ...t empty has not been read for a timeout period and this interrupt is enabled 0 2 RXMIS This bit is 1 if the Rx FIFO is at least half full and this interrupt is enabled 0 3 TXMIS This bit is 1 if the T...

Page 402: ...k I2C1 and I2C2 pins are not fully I2C bus compliant open drain pins but can be configured to be open drain via the PINMODE and PINMODE_OD registers The non compliance is in the I2C bus ability to tur...

Page 403: ...er to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte unless the slave...

Page 404: ...s must be configured in the I2CPADCFG register for Fast Mode Plus The three I2C interfaces are identical except for the pin I O characteristics I2C0 complies with the entire I2C specification supporti...

Page 405: ...ister must be initialized as shown in Table 19 361 I2EN must be set to 1 to enable the I2C function If the AA bit is 0 the I2C interface will not acknowledge any address when another device is master...

Page 406: ...details refer to Table 19 380 When the LPC17xx needs to acknowledge a received byte the AA bit needs to be set accordingly prior to clearing the SI bit and initiating the byte read When the LPC17xx n...

Page 407: ...rface waits until it is addressed by its own address or General Call address followed by the data direction bit If the direction bit is 0 W it enters slave receiver mode If the direction bit is 1 R it...

Page 408: ...e of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that...

Page 409: ...88 I2C serial interface block diagram APB BUS STATUS REGISTER I2CnSTAT CONTROL REGISTER and SCL DUTY CYLE REGISTERS I2CnCONSET I2CnCONCLR I2CnSCLH I2CnSCLL ADDRESS REGISTERS MASK and COMPARE SHIFT RE...

Page 410: ...most significant bits in I2ADR It also compares the first received 8 bit byte with the General Call address 0x00 If an equality is found the appropriate status bits are set and an interrupt is request...

Page 411: ...ag is cleared 7 7 Serial clock generator This programmable clock pulse generator provides the SCL clock pulses when the I2C block is in the master transmitter or master receiver mode It is switched of...

Page 412: ...ay be read as I2CONSET Writing to I2CONSET will set bits in the I2C control register that correspond to ones in the value written Conversely writing to I2CONCLR will clear bits in the I2C control regi...

Page 413: ...gnificant bit determines whether a slave responds to the General Call address R W 0x00 0x4001 C00C I2C0ADR0 0x4005 C00C I2C1ADR0 0x400A 000C I2C2ADR0 I2SCLH SCH Duty Cycle Register High Half Word Dete...

Page 414: ...T shift register will be transferred to the I2DATA_BUFFER automatically after every 9 bits 8 bits of data plus ACK or NACK has been received on the bus RO 0x00 0x4001 C02C I2C0DATA_ BUFFER 0x4005 C02C...

Page 415: ...ock generator If the I2C interface is already in master mode and data has been transmitted or received it transmits a repeated START condition STA may be set at any time including when the I2C interfa...

Page 416: ...Register has been received 2 The General Call address has been received while the General Call bit GC in I2ADR is set 3 A data byte has been received while the I2C is in the master receiver mode 4 A...

Page 417: ...When any of these states entered the SI bit will be set For a complete list of status codes refer to tables from Table 19 379 to Table 19 382 8 4 I2C Data register I2DAT I2C0 I2C0DAT 0x4001 C008 I2C1...

Page 418: ...001C bit description Bit Symbol Value Description Reset value 0 MM_ENA Monitor mode enable 0 0 Monitor mode disabled 1 The I2C module will enter monitor mode In this mode the SDA output will be put i...

Page 419: ...ld not respond to any loss of arbitration state that is detected 8 6 I2C Data buffer register I2DATA_BUFFER I2C0 I2CDATA_BUFFER 0x4001 C02C I2C1 I2C1DATA_BUFFER 0x4005 C02C I2C2 I2C2DATA_BUFFER 0x400A...

Page 420: ...use an automatic compare on the corresponding bit of the received address when it is compared to the I2ADRn register associated with that mask register In other words bits in an I2ADRn register which...

Page 421: ...he frequency of the peripheral bus APB 11 The values for I2SCLL and I2SCLH must ensure that the data rate is in the appropriate I2C data rate range Each register value must be greater than or equal to...

Page 422: ...95 circles are used to indicate when the serial interrupt flag is set The numbers in the circles show the status code held in the I2STAT register At these points a service routine must be executed to...

Page 423: ...0x20 or 0x38 for the master mode and also 0x68 0x78 or 0xB0 if the slave mode was enabled AA logic 1 The appropriate action to be taken for each of these status codes is detailed in Table 19 379 Afte...

Page 424: ...its own slave address followed by the data direction bit which must be 0 W for the I2C block to operate in the slave receiver mode After its own slave address and the W bit have been received the ser...

Page 425: ...entry MR MT to corresponding states in Slave mode A OR A A OR A A other Master continues other Master continues A other Master continues 20H 08H 18H 28H 30H 10H 68H 78H B0H 38H 38H arbitration lost in...

Page 426: ...to corresponding states in Slave mode A R SLA S R SLA S W A A OR A A P other Master continues other Master continues A other Master continues 48H 40H 58H 10H 68H 78H B0H 38H 38H arbitration lost in Sl...

Page 427: ...80H 88H reception of the General Call address and one or more Data bytes arbitration lost as Master and addressed as Slave last data byte received is Not acknowledged arbitration lost as Master and a...

Page 428: ...82 The slave transmitter mode may also be entered if arbitration is lost while the I2C block is in the master mode see state 0xB0 If the AA bit is reset during a transfer the I2C block will transmit t...

Page 429: ...x20 SLA W has been transmitted NOT ACK has been received Load data byte or 0 0 0 X Data byte will be transmitted ACK bit will be received No I2DAT action or 1 0 0 X Repeated START will be transmitted...

Page 430: ...action 1 0 0 X A START condition will be transmitted when the bus becomes free 0x40 SLA R has been transmitted ACK has been received No I2DAT action or 0 0 0 0 Data byte will be received NOT ACK bit w...

Page 431: ...er General Call address has been received ACK has been returned No I2DAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned No I2DAT action X 0 0 1 Data byte will be received an...

Page 432: ...addressed SLV mode Own SLA will be recognized General Call address will be recognized if I2ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 0xA0 A STOP condition or repea...

Page 433: ...ved 0xC0 Data byte in I2DAT has been transmitted NOT ACK has been received No I2DAT action or 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General Call address No I2DAT acti...

Page 434: ...occurs between other states and when the I2C block is not involved in a serial transfer 9 5 2 I2STAT 0x00 This status code indicates that a bus error has occurred during an I2C serial transfer A bus...

Page 435: ...f arbitration is indicated by the following states in I2STAT 0x38 0x68 0x78 and 0xB0 see Figure 19 91 and Figure 19 92 If the STA flag in I2CON is set by the routines which service these states then i...

Page 436: ...ansmitting additional clock pulses on the SCL line Figure 19 97 The I2C interface does not include a dedicated timeout timer to detect an obstructed bus but this can be implemented using another timer...

Page 437: ...is enabled for both master and slave modes For each mode a buffer is used for transmission and reception The initialization routine performs the following functions I2ADR is loaded with the part s ow...

Page 438: ...ating modes are not used the associated state services can be omitted as long as care is taken that the those states can never occur In an application it may be desirable to implement some kind of tim...

Page 439: ...mode specific states 10 5 1 State 0x00 Bus Error Enter not addressed Slave mode and release bus 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit...

Page 440: ...ter Transmit buffer pointer 5 Exit 10 6 2 State 0x20 Slave Address Write has been transmitted NOT ACK has been received A STOP condition will be transmitted 1 Write 0x14 to I2CONSET to set the STO and...

Page 441: ...0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 10 7 2 State 0x48 Slave Address Read has been transmitted NOT ACK has been received A STOP condition will be tra...

Page 442: ...R W bit as bus Master Own Slave Address Write has been received ACK has been returned Data will be received and ACK will be returned STA is set to restart Master mode after the bus is free again 1 Wri...

Page 443: ...ously addressed with own Slave Address Data has been received and NOT ACK has been returned Received data will not be saved Not addressed Slave mode is entered 1 Write 0x04 to I2CONSET to set the AA b...

Page 444: ...tate 0xB0 Arbitration lost in Slave Address and R W bit as bus Master Own Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received STA is set to res...

Page 445: ...A F T D R A UM10360_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 445 of 808 NXP Semiconductors UM10360 Chapter 19 LPC17xx I2C0 1 2 interface 10 9 5 State 0xC8 The last data by...

Page 446: ...elect signal The basic I2S connection has one master which is always the master and one slave The I2S interface on the LPC17xx provides a separate transmit and receive channel each of which can operat...

Page 447: ...from the relevant bus pin When an I2S bus is active the word select receive clock and transmit clock signals are sent continuously by the bus master while data is sent continuously by the transmitter...

Page 448: ...it Word Select Selects the channel to which data is being sent It is driven by the master and received by the slave Corresponds to the signal WS in the I2S bus specification WS 0 indicates that data i...

Page 449: ...r FIFO RO 0 0x400A 800C I2SSTATE Status Feedback Register Contains status information about the I2S interface RO 0 0x400A 8010 I2SDMA1 DMA Configuration Register 1 Contains control information for DMA...

Page 450: ...ster mode when 1 slave mode See Section 20 7 for a summary of useful combinations for this bit with I2STXMODE 1 14 6 ws_halfperiod Word select half period minus one i e WS 64clk period ws_halfperiod 3...

Page 451: ...its in I2SDMA1 are shown in Table 20 391 Refer to the General Purpose DMA Controller chapter for details of DMA operation Table 388 Transmit FIFO register I2STXFIFO address 0x400A 8008 bit description...

Page 452: ...MA1 0 15 13 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 20 16 tx_depth_dma1 Set the FIFO level that triggers a transmit DMA reque...

Page 453: ...then no clock is generated 15 13 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 20 16 tx_depth_Irq Set the FIFO level on which to cr...

Page 454: ...Receive Clock Rate register I2SRXRATE address 0x400A 8024 bit description Bit Symbol Description Reset Value 7 0 Y_divider I2S receive MCLK rate denominator This value is used to divide PCLK to produ...

Page 455: ...ter I2STXMODE 0x400A 8030 bit description Bit Symbol Value Description Reset Value 1 0 TXCLKSEL Clock source selection for the transmit bit clock divider 0 00 Select the TX fractional rate divider clo...

Page 456: ...ufficient data has been written in the transmit FIFO Note that when stopped data output is muted All data accesses to FIFOs are 32 bits Figure 20 111 shows the possible data sequences A data sample in...

Page 457: ...0 4 wire transmitter master mode sharing the receiver bit clock and WS See Figure 20 101 The I2S transmit function operates as a master The transmit clock source is the RX bit clock The WS used is th...

Page 458: ...STX_SDA I2STX_CLK TX_REF TX bit clock I2STX_RATE 7 0 I2STX_RATE 15 8 Pin OE TX_WS ref Fig 100 Transmitter master mode sharing the receiver reference clock N 1 to 64 I2STXBITRATE 5 0 I2STX_WS I2STX_SDA...

Page 459: ...ternally generated RX_WS The RX_MCLK pin is not enabled for output 0 0 1 0 0 4 wire receiver master mode sharing the transmitter bit clock and WS See Figure 20 107 The I2S receive function operates as...

Page 460: ...I2SRX_SDA I2SRX_CLK RX_REF RX bit clock I2SRX_RATE 7 0 I2SRX_RATE 15 8 Pin OE RX_WS ref Fig 106 Receiver master mode sharing the transmitter reference clock N 1 to 64 I2SRXBITRATE 5 0 I2SRX_WS I2SRX_S...

Page 461: ...gister System signaling occurs when a level detection is true and enabled Fig 110 4 wire receiver slave mode sharing the transmitter bit clock and WS I2SRX_WS I2SRX_SDA TX bit clock TX_WS ref I2 S per...

Page 462: ...ed User manual Rev 00 06 5 June 2009 462 of 808 NXP Semiconductors UM10360 Chapter 20 LPC17xx I2S interface Fig 111 FIFO contents for various I2S modes LEFT 1 7 0 RIGHT 1 7 0 LEFT 7 0 RIGHT 7 0 Stereo...

Page 463: ...ed in the NVIC using the appropriate Interrupt Set Enable register 5 DMA Up to two match conditions can be used to generate timed DMA requests see Table 31 525 2 Features Remark The four Timer Counter...

Page 464: ...are driven identically When more than one pin is selected for a CAP input the pin with the lowest Port number is used Note that match conditions may be used internally without the use of a device pin...

Page 465: ...T1PR 0x4000 800C T2PR 0x4009 000C T3PR 0x4009 400C PC Prescale Counter The 32 bit PC is a counter which is incremented to the value stored in PR When the value in PR is reached the TC is incremented...

Page 466: ...0 is loaded with the value of TC when there is an event on the CAPn 0 CAP0 0 or CAP1 0 respectively input RO 0 T0CR0 0x4000 402C T1CR0 0x4000 802C T2CR0 0x4009 002C T3CR0 0x4009 402C CR1 Capture Regis...

Page 467: ...not exceed one quarter of the PCLK clock Consequently duration of the high low levels on the same CAP input in this case can not be shorter than 1 2 PCLK Table 408 Timer Control Register TCR TIMERn T...

Page 468: ...of the timer versus the maximum time before the timer overflows The Prescale Counter is incremented on every PCLK When it reaches the value stored in the Prescale register the Timer Counter is increme...

Page 469: ...n MR0 the TC and PC will be stopped and TCR 0 will be set to 0 if MR0 matches the TC 0 0 Feature disabled 3 MR1I 1 Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC 0 0 T...

Page 470: ...esents the Timer number 0 or 1 Note If Counter mode is selected for a particular CAP input in the CTCR the 3 bits for that input in this register should be programmed as 000 but capture and or interru...

Page 471: ...1 pin in a positive logic manner 0 low 1 high 0 2 EM2 External Match 2 When a match occurs between the TC and MR2 this bit can either toggle go low go high or do nothing depending on bits 9 8 of this...

Page 472: ...en it is acted upon by the GPDMA controller 7 Example timer operation Figure 21 112 shows a timer configured to reset the count and generate an interrupt on match The prescaler is set to 2 and the mat...

Page 473: ...itecture The block diagram for TIMER COUNTER0 and TIMER COUNTER1 is shown in Figure 21 114 Fig 114 Timer block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enabl...

Page 474: ...stored in used bits only It does not include content of reserved bits 3 1 RI Compare Value register RICOMPVAL 0x400B 0000 3 2 RI Mask register RIMASK 0x400B 0004 UM10360 Chapter 22 LPC17xx Repetitive...

Page 475: ...Table 417 RI Control register RICTRL address 0x400B 0008 bit description Bit Symbol Value Description Reset value 0 RITINT Interrupt flag 0 1 This bit is set to 1 by hardware whenever the counter valu...

Page 476: ...Enable_Break bit RICTRL 1 is set Both the Enable_Timer and Enable_Break bits are set on reset The interrupt flag can be cleared in software by writing a 1 to the Interrupt bit RICTRL 0 Software can lo...

Page 477: ...ting system or other system management software Since the System Tick Timer is a part of the Cortex M3 it facilitates porting of software by providing a standard timer that is available on Cortex M3 b...

Page 478: ...SOURCE TICKINT COUNTFLAG load under flow count enable clock D Q load data Table 419 System Tick Timer register map Name Description Access Reset value 1 Address STCTRL System Timer Control and status...

Page 479: ...00 MHz This is the intended use of the System Tick Timer by ARM It can be used to generate interrupts at other frequencies by selecting the correct reload value 15 3 Reserved user software should not...

Page 480: ...his value initialized at reset with a factory supplied value selected for the LPC17xx The provided values of TENMS SKEW and NOREF are applicable only when using a CPU clock or external STCLK source of...

Page 481: ...on with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Supports single edge controlled and or dou...

Page 482: ...sed to provide a single edge controlled PWM output One match register PWMMR0 controls the PWM cycle rate by resetting the count upon match The other match register controls the PWM edge position Addit...

Page 483: ...GISTER 2 LOAD ENABLE SHADOW REGISTER 0 LOAD ENABLE SHADOW REGISTER 5 LOAD ENABLE SHADOW REGISTER 4 LOAD ENABLE LOAD ENABLE REGISTER CLEAR Match0 SHADOW REGISTER 1 LOAD ENABLE MATCH CONTROL REGISTER IN...

Page 484: ...er Essentially PWM1 cannot be a double edged output 2 It is generally not advantageous to use PWM channels 3 and 5 for double edge PWM outputs because it would reduce the number of double edge PWM out...

Page 485: ...PWM cycle has the same effect as a request for a falling edge at the end of a PWM cycle 3 When match values are changing if one of the old match values is equal to the PWM rate it is used again once i...

Page 486: ...PR When the value in PR is reached the TC is incremented The PC is observable and controllable through the bus interface R W 0 PWM1PC 0x4001 8010 MCR Match Control Register The MCR is used to control...

Page 487: ...set the TC stop both the TC and PC and or generate an interrupt when it matches the TC In addition a match between this value and the TC clears PWM4 in either edge mode and sets PWM5 if it s in double...

Page 488: ...e ones to reserved bits The value read from a reserved bit is not defined NA Table 428 PWM Interrupt Register PWM1IR address 0x4001 8000 bit description Bit Symbol Description Reset Value Table 429 PW...

Page 489: ...nted on both edges of the PCAP input selected by bits 3 2 3 2 Count Input Select When bits 1 0 of this register are not 00 these bits select which PCAP pin which carries the signal used to increment t...

Page 490: ...PWMMR3S 1 Stop on PWMMR3 The PWMTC and PWMPC will be stopped and PWMTCR 0 will be set to 0 if PWMMR3 matches the PWMTC 0 0 This feature is disabled 12 PWMMR4I 1 Interrupt on PWMMR4 An interrupt is gen...

Page 491: ...0 if PWMMR6 matches the PWMTC 0 31 21 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 431 Match Control Register PWM1MCR addres...

Page 492: ...course of the next PWM cycle Once the transfer of new Table 433 PWM Control Register PWM1PCR address 0x4001 804C bit description Bit Symbol Value Description Rese t Value 1 0 Unused Unused always zer...

Page 493: ...ctive when the timer is next reset by a PWM Match event See Section 24 7 4 PWM Match Control Register PWM1MCR 0x4001 8014 0 1 Enable PWM Match 1 Latch Writing a one to this bit allows the last value w...

Page 494: ...it Timer Counter TC a 32 bit Limit register LIM a 32 bit Match register MAT a 10 bit dead time register DT and an associated 10 bit dead time counter a 32 bit capture register CAP two modulated output...

Page 495: ...2 Clock selection Clock selection TC0 Event selection TC1 Event selection TC2 Event selection MCCNTCON MCCAPCON MAT0 oper MAT0 write LIM0 oper LIM0 write CAP0 channel output control dead time counter...

Page 496: ...register that is incremented by a processor clock timer mode or by an input pin counter mode Each channel has a Limit register that is compared to the TC value and when a match occurs the TC is recycl...

Page 497: ...ol set address WO 0x400B 8010 MCCAPCON_CLR Event Control clear address WO 0x400B 8014 MCTC0 Timer Counter register channel 0 R W 0 0x400B 8018 MCTC1 Timer Counter register channel 1 R W 0 0x400B 801C...

Page 498: ...1 CENTER0 Edge center aligned operation for channel 0 0 0 Edge aligned 1 Center aligned 2 POLA0 Selects polarity of the MCOA0 and MCOB0 pins 0 0 Passive state is LOW active state is HIGH 1 Passive st...

Page 499: ...1 Dead time enabled 20 DISUP2 Enable disable updates of functional registers for channel 2 see Section 25 8 2 0 0 Functional registers are updated from the write registers at the end of each PWM cycle...

Page 500: ...dress sets the corresponding bits in the MCCON register See Table 25 437 for the bit allocation Table 439 MCPWM Control clear address MCCON_CLR 0x400B 8008 bit description Bit Description 31 0 Writing...

Page 501: ...lling edge on MCI1 0 16 CAP2MCI2_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2 0 17 CAP2MCI2_FE A 1 in this bit enables a channel 2 capture event on a falling edge on M...

Page 502: ...ts in MCINTEN thus disabling interrupts 7 3 3 MCPWM Interrupt Enable clear address MCINTEN_CLR 0x400B 8058 Writing ones to this write only address clears the corresponding bits in MCINTEN thus enablin...

Page 503: ...ress sets the corresponding bit s in MCINTF thus clearing the corresponding interrupt request s This is typically done in interrupt service routines Table 447 PWM interrupt enable clear register MCINT...

Page 504: ...ter 0 1 TC0MCI0_FE 1 If MODE0 is 1 counter 0 advances on a falling edge on MCI0 0 0 A falling edge on MCI0 does not affect counter 0 2 TC0MCI1_RE 1 If MODE0 is 1 counter 0 advances on a rising edge on...

Page 505: ...on MCI0 0 0 A falling edge on MCI0 does not affect counter 2 14 TC2MCI1_RE 1 If MODE2 is 1 counter 2 advances on a rising edge on MCI1 0 0 A rising edge on MCI1 does not affect counter 2 15 TC2MCI1_FE...

Page 506: ...ate If the channel s CENTER and DTE bits in MCCON are both 0 the match simultaneously switches the channel s B output from passive to active state If the channel s CENTER bit is 0 but the DTE bit is 1...

Page 507: ...If the channel s CENTER and DTE bits in MCCON are both 0 the match simultaneously switches the channel s A output from passive to active state If the channel s CENTER bit is 0 but the DTE bit is 1 the...

Page 508: ...in a motor control application take longer to fully turn off than they take to start to turn on If the A and B transistors are ever turned on at the same time a wasteful and damaging current will flow...

Page 509: ...ime the two outputs have opposite polarity but a dead time feature can be enabled on a per channel basis to delay both signals transitions from passive to active state so that the transistors are neve...

Page 510: ...s A passive until the TC matches the Match register at which point it changes to A active When the TC matches the Limit register the MCO state changes back to A passive and the TC is reset and starts...

Page 511: ...value in the MCDT register to 0 whenever the channel s A or B output changes from active to passive The transition of the other output from passive to active is delayed until the dead time counter rea...

Page 512: ...upt flag is cleared or the Abort interrupt is disabled The ABORT flag may not be cleared before the MCABORT input goes high 8 4 Capture events Each PWM channel can take a snapshot of its TC when an in...

Page 513: ...B output pins are inverted when the INVBDC bit is 1 in the MCCON register This feature accommodates bridge drivers that have active low inputs for the low side switches The MCCP register is implemente...

Page 514: ...MAT registers The LIM1 2 registers are not used Each channel controls its MCO output by comparing its MAT value to TC0 Figure 25 125 shows sample waveforms for the six MCO outputs in three phase AC m...

Page 515: ...channel s TC matches its Limit register When any channel captures the value of its TC into its Capture register because a selected edge occurs on any of MCI0 2 When all three channels outputs are for...

Page 516: ...capture using built in timer velocity compare function with less than interrupt uses 32 bit registers for position and velocity three position compare registers with interrupts index counter for revol...

Page 517: ...Fig 126 Encoder interface block diagram 002aad520 index Ph A Ph B PCLK DIGITAL FILTER QUAD DECODER VELOCITY TIMER velocity interrupt TIM_Int low velocity interrupt LVEL_Int encoder clock interrupt EN...

Page 518: ...SigMode bit of the QEI Control QEICON register See Table 26 466 When the SigMode bit 1 the quadrature decoder is bypassed and the PhA pin functions as the direction signal and PhB pin functions as th...

Page 519: ...in the positional counter The position integrator and velocity capture can be independently enabled Alternatively the phase signals can be interpreted as a clock and direction signal as output by some...

Page 520: ...per second If the timer were clocked at 10 000 Hz and the loadvalue was 2 500 of a second it would count 20 480 pulses per update Using the above equation RPM 10000 1 20480 60 2500 2048 4 600 RPM Now...

Page 521: ...r Position index and timer registers QEIPOS 0x400B C00C R Position register QEIMAXPOS 0x400B C010 R W Maximum position register CMPOS0 0x400B C014 R W position compare register 0 CMPOS1 0x400B C018 R...

Page 522: ...t position counter on index When set 1 resets the position counter to all zeros when an index pulse occurs Autoclears when the position counter is cleared 0 2 RESV Reset velocity When set 1 resets the...

Page 523: ...on compare value This value is compared against the current value of the position register Interrupts can be enabled to interrupt when the compare value is less than equal to or greater than the curre...

Page 524: ...city timer When this timer overflows the value of velocity counter QEIVEL is stored in the velocity capture register QEICAP the velocity counter is reset to zero the timer is reloaded with the value s...

Page 525: ...this compare register a velocity compare interrupt VELC_Int will be asserted if enabled 6 3 13 QEI Digital Filter register FILTER 0x400B C03C This register contains the sampling count for the digital...

Page 526: ...ed velocity is less than compare velocity 0 3 DIR_Int Indicates that a change of direction was detected 0 4 ERR_Int Indicates that an encoder phase error was detected 0 5 ENCLK_Int Indicates that and...

Page 527: ...velocity is less than compare velocity 0 3 DIR_Int Indicates that a change of direction was detected 0 4 ERR_Int Indicates that an encoder phase error was detected 0 5 ENCLK_Int Indicates that and enc...

Page 528: ...aptured velocity is less than compare velocity 0 3 DIR_Int Indicates that a change of direction was detected 0 4 ERR_Int Indicates that an encoder phase error was detected 0 5 ENCLK_Int Indicates that...

Page 529: ...velocity is less than compare velocity 0 3 DIR_Int Indicates that a change of direction was detected 0 4 ERR_Int Indicates that an encoder phase error was detected 0 5 ENCLK_Int Indicates that and en...

Page 530: ...ured velocity is less than compare velocity 0 3 DIR_EN Indicates that a change of direction was detected 0 4 ERR_EN Indicates that an encoder phase error was detected 0 5 ENCLK_EN Indicates that and e...

Page 531: ...rection was detected 0 4 ERR_EN Indicates that an encoder phase error was detected 0 5 ENCLK_EN Indicates that and encoder clock pulse was detected 0 6 POS0_Int Indicates that the position 0 compare v...

Page 532: ...e CPU power supply when it is present 20 bytes of Battery backed storage and RTC operation when power is removed from the CPU Dedicated 32 kHz ultra low power oscillator Dedicated battery power supply...

Page 533: ...Clock RTC and backup registers 4 Architecture Fig 128 RTC domain conceptual diagram Fig 129 RTC functional block diagram VBAT pin Ultra low power regulator Power selector VDD REG 3v3 pin Ultra low po...

Page 534: ...88 RTC pin description Name Type Description RTCX1 I Input to the RTC oscillator circuit RTCX2 O Output from the RTC oscillator circuit Remark If the RTC is not used the RTCX1 2 pins can be left float...

Page 535: ...interrupt to be generated The AMR provides a mechanism to mask alarm compares If all non masked alarm registers match the value in their corresponding time counter then an interrupt is generated The R...

Page 536: ...ement Interrupt block generated an interrupt Writing a one to this bit location clears the counter increment interrupt 0 1 RTCALF When one the alarm registers generated an interrupt Writing a one to t...

Page 537: ...tions that are not part of the Real Time Clock itself the part recording the passage of time and generating other time related functions On the LPC17xx the only added interrupt flag is for failure of...

Page 538: ...4 The Consolidated Time Register 0 contains the low order time values Seconds Minutes Hours and Day of Week Table 494 RTC Auxiliary control register RTC_AUX address 0x4002 405C bit description Bit Sym...

Page 539: ...read from a reserved bit is not defined NA 20 16 Hours Hours value in the range of 0 to 23 NC 23 21 Reserved user software should not write ones to reserved bits The value read from a reserved bit is...

Page 540: ...of the month of February for the month day of month and year counters 6 4 2 Calibration register CALIBRATION address 0x4002 4040 The following register is used to calibrate the time counter Table 499...

Page 541: ...and CCALEN 0 In the CALIBRATION register set the calibration value CALVAL 1 and select CALDIR 1 The SEC timer and the calibration counter count up for every 1 Hz clock cycle When the calibration coun...

Page 542: ...0 on page 537 alarm registers match their corresponding time counters then an interrupt is generated The interrupt is cleared when a 1 is written to bit 1 of the Interrupt Location Register ILR 1 7 RT...

Page 543: ...nents and wiring The Watchdog timer can be configured to run in Deep Sleep mode when using the IRC as the clock source 2 Applications The purpose of the Watchdog is to reset the microcontroller within...

Page 544: ...es on the logic in the WDCLK clock domain When the watchdog timer is counting on WDCLK the synchronization logic will first lock the value of the counter on WDCLK and then synchronize it with the PCLK...

Page 545: ...lue Every time a feed sequence occurs the WDTC content is reloaded in to the Watchdog timer It s a 32 bit register with 8 LSB set to 1 on reset Writing values below 0xFF will cause 0x0000 00FF to be l...

Page 546: ...ence 4 4 Watchdog Timer Value register WDTV 0x4000 000C The WDTV register is used to read the current value of Watchdog timer When reading the value of the 32 bit timer the lock and synchronization pr...

Page 547: ...elect the clock source for the Watchdog timer as described below Warning Improper setting of this value may result in incorrect operation of the Watchdog timer which could adversely affect system oper...

Page 548: ...0_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 548 of 808 NXP Semiconductors UM10360 Chapter 28 LPC17xx Watchdog Timer WDT Fig 130 Watchdog block diagram WDTC 32 BIT DOWN COUNT...

Page 549: ...ts To enable interrupts in the ADC see Table 29 517 Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register Disable the ADC interrupt in the NVIC using the appropriate I...

Page 550: ...3V3 if the ADC and DAC are not used VDDA VSSA Power Analog Power and Ground These should be nominally the same voltages as VDD and VSS but should be isolated to minimize noise and error Note this pin...

Page 551: ...rolled mode only one of these bits should be 1 In hardware scan mode any value containing 1 to 8 ones is allowed All zeroes is equivalent to 0x01 0x01 15 8 CLKDIV The APB clock PCLK_ADC0 is divided by...

Page 552: ...ted by bit 27 occurs on MAT0 3 Note that it is not possible to cause the MAT0 3 function to appear on a device pin 110 Start conversion when the edge selected by bit 27 occurs on MAT1 0 Note that this...

Page 553: ...value Table 515 A D Status register AD0INTEN address 0x4003 400C bit description Bit Symbol Value Description Reset value 0 ADINTEN0 0 Completion of a conversion on ADC channel 0 will not generate an...

Page 554: ...ion representing the voltage on the ADn pin divided by the voltage on the VREF pin V VREF Zero in the field indicates that the voltage on the AIN pin was less than equal to or close to that on VSSA wh...

Page 555: ...DONE bit is 1 Software can use the Interrupt Enable bit for the A D Converter in the NVIC to control whether this assertion results in an interrupt DONE is negated when the ADDR is read 11 OVERRUN3 Th...

Page 556: ...rdware from the associated pin whenever a digital function is selected on that pin 6 4 DMA control A DMA transfer request is generated from the ADC interrupt request line To generate a DMA transfer th...

Page 557: ...o analog converter Resistor string architecture Buffered output Power down mode Selectable speed vs power 3 Pin description Table 30 519 gives a brief summary of each of DAC related pins Remark When t...

Page 558: ...ance value greater than that value will cause settling time longer than the specified time One or more graph s of load impedance vs settling time will be included in the final data sheet 4 2 D A Conve...

Page 559: ...it is set in the DACCTRL register the DAC DMA request will be routed to the GPDMA When the DMA_ENA bit is cleared the default state after a reset DAC DMA requests are blocked Table 522 D A Control reg...

Page 560: ...s register address with the DACR register The DACR itself will be loaded from the pre buffer whenever the counter reaches zero and the DMA request is set At the same time the counter is reloaded with...

Page 561: ...A channels Each channel can support an unidirectional transfer 16 DMA request lines Single DMA and burst DMA request signals Each peripheral connected to the DMA Controller can assert either a burst D...

Page 562: ...operate in Sleep mode Note that in Sleep mode the GPDMA cannot access the flash memory 4 Functional description This section describes the major functional blocks of the DMA Controller 4 1 DMA control...

Page 563: ...troller contains one AHB master interface The AHB master is capable of dealing with all types of AHB transactions including Split retry and error responses from slaves If a peripheral performs a split...

Page 564: ...Little 8 16 1 7 0 2 15 8 3 23 16 4 31 24 21 43 65 87 1 15 0 2 31 16 43214321 87658765 Little Little 8 32 1 7 0 2 15 8 3 23 16 4 31 24 21 43 65 87 1 31 0 87654321 Little Little 16 8 1 7 0 1 15 8 2 23...

Page 565: ...ked Big Big 8 16 1 31 24 2 23 16 3 15 8 4 7 0 12 34 56 78 1 15 0 2 31 16 12341234 56785678 Big Big 8 32 1 31 24 2 23 16 3 15 8 4 7 0 12 34 56 78 1 31 0 12345678 Big Big 16 8 1 31 24 1 23 16 2 15 8 2 7...

Page 566: ...ut is generated as an OR function of the individual interrupt requests of the DMA Controller and is connected to the interrupt controller 4 2 DMA system connections 4 2 1 DMA request signals The DMA r...

Page 567: ...aspects of how source peripherals relate to the DMA Controller There are also global DMA control and status registers The DMA Controller registers are shown in Table 31 526 Table 525 DMA Connections P...

Page 568: ...1 registers DMACC1SrcAddr DMA Channel 1 Source Address Register 0 R W 0x5000 4120 DMACC1DestAddr DMA Channel 1 Destination Address Register 0 R W 0x5000 4124 DMACC1LLI DMA Channel 1 Linked List Item R...

Page 569: ...5 Linked List Item Register 0 R W 0x5000 41A8 DMACC5Control DMA Channel 5 Control Register 0 R W 0x5000 41AC DMACC5Config DMA Channel 5 Configuration Register 0 1 R W 0x5000 41B0 Channel 6 registers...

Page 570: ...ta bits that are 0 have no effect on the corresponding bit in the register Table 31 531 shows the bit assignments of the DMACIntErrClr Register Table 528 DMA Interrupt Terminal Count Request Status re...

Page 571: ...nabled as indicated by the Enable bit in the DMACCxConfig Register A 1 bit indicates that a DMA channel is enabled A bit is cleared on completion of the DMA transfer Table 31 534 shows the bit assignm...

Page 572: ...saction has completed Reading the register indicates which sources are requesting single DMA transfers A request can be generated from either a peripheral or the software request register Table 31 536...

Page 573: ...e requesting last single DMA transfers A request can be generated from either a peripheral or the software request register Table 31 538 shows the bit assignments of the DMACSoftLSReq Register 5 13 DM...

Page 574: ...gnments of the DMAReqSel Register Table 539 DMA Configuration register DMACConfig 0x5000 4030 Bit Name Function 0 E DMA Controller enable 0 disabled default Disabling the DMA Controller reduces power...

Page 575: ...d When the DMA channel is enabled this register is updated As the source address is incremented By following the linked list when a complete packet of data has been transferred Reading the register wh...

Page 576: ...registers DMACCxLLI 0x5000 41x8 The eight read write DMACCxLLI Registers DMACC0LLI to DMACC7LLI contain a word aligned address of the next Linked List Item LLI If the LLI is 0 then the current LLI is...

Page 577: ...his field sets the size of the transfer The transfer size value must be set before the channel is enabled Transfer size is updated as data transfers are completed A read from this field indicates the...

Page 578: ...3 21 DWidth Destination transfer width Transfers wider than the AHB master bus width are not supported The source and destination widths can be different from each other The hardware automatically pac...

Page 579: ...reaches 0 indicating that there is no data left in the FIFO Finally the Channel Enable bit can be cleared 5 1 SrcPeripheral Source peripheral This value selects the DMA source request peripheral This...

Page 580: ...e fetch followed by a destination drain back to back 5 21 2 Transfer type Table 31 547 lists the bit values of the transfer type bits identified in Table 31 546 6 Using the DMA controller 6 1 Programm...

Page 581: ...d Clear the channel enable bit in the relevant channel configuration register 6 1 5 Setting up a new DMA transfer To set up a new DMA transfer If the channel is not set aside for the DMA transaction 1...

Page 582: ...to memory Peripheral to peripheral Table 31 548 indicates the request signals used for each type of transfer 6 2 1 Peripheral to memory or memory to peripheral DMA flow For a peripheral to memory or m...

Page 583: ...t reaching 0 The DMA Controller responds with a DMA acknowledge to the source peripheral Further source DMA requests are ignored 7 When the destination DMA request goes active and there is data in the...

Page 584: ...single register to enable the source of an interrupt to be found quickly Writing to the DMACIntTCClear or the DMACIntErrClr Registers with a bit set to 1 enables selective clearing of interrupts 6 3 1...

Page 585: ...equired the DMACCxLLI Register must be set to 0 The source and destination data areas are defined by a series of linked lists Each Linked List Item LLI controls the transfer of one block of data and t...

Page 586: ...request must then be serviced and the relevant bit in the DMACIntTCClear Register must be set to clear the interrupt 6 5 1 2 Example of scatter gather DMA See Figure 31 133 for an example of an LLI A...

Page 587: ...tialize the DMA stream the first LLI 0x20000 is programmed into the DMA Controller When the first packet of data has been transferred the next LLI is automatically loaded The final LLI is stored at 0x...

Page 588: ...minal levels when the rising edge on RESET pin is generated it may take up to 3 ms before P2 10 is sampled and the decision on whether to continue with user code or ISP handler is made If P2 10 is sam...

Page 589: ...o baud routine synchronizes with the host via serial port 0 The host should send a 0x3F as a synchronization character and wait for a response The host side serial port settings should be 8 data bits...

Page 590: ...and received in UU encoded format 3 2 1 ISP command format Command Parameter_0 Parameter_1 Parameter_n CR LF Data Data only for Write commands 3 2 2 ISP response format Return_Code CR LF Response_0 C...

Page 591: ...active The user should either disable interrupts or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM before making a flash erase write IAP call The IA...

Page 592: ...ming 4 Boot process flowchart 1 For details on handling the crystal frequency see Section 32 8 9 Re invoke ISP on page 608 2 For details on available ISP commands based on the CRP settings see Section...

Page 593: ...x x x 2 4 0X0000 2000 0X0000 2FFF x x x x x 3 4 0X0000 3000 0X0000 3FFF x x x x x 4 4 0X0000 4000 0X0000 4FFF x x x x x 5 4 0X0000 5000 0X0000 5FFF x x x x x 6 4 0X0000 6000 0X0000 6FFF x x x x x 7 4...

Page 594: ...commands and restrictions Write to RAM command can not access RAM below 0x10000200 This is due to use of the RAM by the ISP code see Section 32 3 2 7 Copy RAM to Flash command can not write to Sector...

Page 595: ...the host Exceptions from this rule are Set Baud Rate Write to RAM Read Memory and Go commands Table 551 Code Read Protection hardware software interaction CRP option User Code Valid P2 10 pin at rese...

Page 596: ...bed in Table 553 ISP Unlock command Command U Input Unlock code 2313010 Return Code CMD_SUCCESS INVALID_CODE PARAM_ERROR Description This command is used to unlock Flash Write Erase and Go commands Ex...

Page 597: ...s The data stream is followed by the command success return code The check sum is sent after transmitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and...

Page 598: ...of Bytes Number of bytes to be read Count should be a multiple of 4 Return Code CMD_SUCCESS followed by actual data UU encoded ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte...

Page 599: ...4 4096 SECTOR_NOT_PREPARED_FOR WRITE_OPERATION BUSY CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to program the flash memory The Prepare Sector s for Write Oper...

Page 600: ...or s of on chip flash memory This command only allows erasure of all user sectors when the code read protection is enabled Example E 2 3 CR LF erases the flash sectors 2 and 3 Table 563 ISP Blank chec...

Page 601: ...0x13733 LPC1764 71970 0x11922 LPC1758 81716 0x13F34 LPC1756 71459 0x11723 LPC1754 71458 0x11722 LPC1752 4385 0x01121 LPC1751 4368 0x01110 Table 566 ISP Read Boot Code version number command Command K...

Page 602: ...4 CR LF compares 4 bytes from the RAM address 0x1000 0200 to the 4 bytes from the flash address 0x2000 Table 569 ISP Return Codes Summary Return Code Mnemonic Description 0 CMD_SUCCESS Command is exe...

Page 603: ...results is 4 returned by the Read device serial number command The command handler sends the status code INVALID_COMMAND when an undefined command is received The IAP routine resides at location 0x1F...

Page 604: ...ameters can be returned in the r0 r1 r2 and r3 registers respectively Additional parameters are returned indirectly via memory Some of the IAP calls require more than 4 parameters If the ARM suggested...

Page 605: ...1 PARAMETER 2 PARAMETER n STATUS CODE RESULT 1 RESULT 2 RESULT n command parameter table command result table ARM REGISTER r0 ARM REGISTER r1 Table 571 IAP Prepare sector s for write operation command...

Page 606: ...kHz Return Code CMD_SUCCESS SRC_ADDR_ERROR Address not a word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 256 512 102...

Page 607: ...the Status Code is SECTOR_NOT_BLANK Result1 Contents of non blank word location Description This command is used to blank check a sector or multiple sectors of on chip flash memory To blank check a s...

Page 608: ...Identification Number Description This command is used to read the device identification number The serial number may be used to uniquely identify a single unit among all LPC17xx devices Table 578 IAP...

Page 609: ...should pass the CCLK crystal or PLL output depending on the clock source selection Section 4 4 1 frequency after autobaud handshake Another option is to disable the PLL and select the IRC as the cloc...

Page 610: ...ace functions The ARM Cortex M3 is configured to support up to eight breakpoints and four watchpoints 3 Description Debugging with the LPC17xx defaults to JTAG Once in the JTAG debug mode the debug to...

Page 611: ...gic RTCK Output JTAG Returned Test Clock This is an extra signal added to the JTAG port and is included for backward pin compatibility with LPC23xx series devices that share the same pinout as this de...

Page 612: ...his causes power modes at the device level to be different from normal modes operation These differences mean that power measurements should not be made while debugging the results will be higher than...

Page 613: ...ormance combined with fast interrupt handling enhanced system debug with extensive breakpoint and trace capabilities efficient processor core system and memories ultra low power consumption with integ...

Page 614: ...des that include a deep sleep function that enables the entire device to be rapidly powered down LPC17xx devices support additional reduced power modes see Section 4 8 Power control for details 1 1 1...

Page 615: ...sion and fast multiplier deterministic high performance interrupt handling for time critical applications optional memory protection unit MPU for safety critical applications extensive debug and trace...

Page 616: ...ADD ADDS Rd Rn Op2 Add N Z C V Section 34 2 5 1 ADD ADDW Rd Rn imm12 Add N Z C V Section 34 2 5 1 ADR Rd label Load PC relative address Section 34 2 4 1 AND ANDS Rd Rn Op2 Logical AND N Z C Section 3...

Page 617: ...Shift Left N Z C Section 34 2 5 3 LSR LSRS Rd Rm Rs n Logical Shift Right N Z C Section 34 2 5 3 MLA Rd Rn Rm Ra Multiply with Accumulate 32 bit result Section 34 2 6 1 MLS Rd Rn Rm Ra Multiply and Su...

Page 618: ...STREXB Rd Rt Rn Store Register Exclusive byte Section 34 2 4 8 STREXH Rd Rt Rn Store Register Exclusive halfword Section 34 2 4 8 STRH STRHT Rt Rn offset Store Register halfword Section 34 2 4 STRT R...

Page 619: ...ctions give more information about using the instructions Table 585 CMSIS intrinsic functions to generate some Cortex M3 instructions Instruction CMSIS intrinsic function CPSIE I void __enable_irq voi...

Page 620: ...in some instructions are flexible in that they can either be a register or a constant See Section 34 2 3 3 2 3 2 Restrictions when using PC or SP Many instructions have restrictions on whether you ca...

Page 621: ...gister with optional shift You specify an Operand2 register in the form Rm shift where Rm is the register holding the data for the second operand shift is an optional shift to be applied to Rm It can...

Page 622: ...eft hand n bits of the result See Figure 34 138 You can use the ASR n operation to divide the value in the register Rm by 2n with the result being rounded towards negative infinity When the instructio...

Page 623: ...teger Overflow can occur without warning When the instruction is LSLS or when LSL n with non zero n is used in Operand2 with the instructions MOVS MVNS ANDS ORRS ORNS EORS BICS TEQ or TST the carry fl...

Page 624: ...nto bit 31 of the result See Figure 34 142 When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS MVNS ANDS ORRS ORNS EORS BICS TEQ or TST the carry flag is updated to...

Page 625: ...might permit other syntaxes for PC relative expressions such as a label plus or minus a number or an expression of the form PC number 2 3 7 Conditional execution Most data processing instructions can...

Page 626: ...gister A carry occurs if the result of an addition is greater than or equal to 232 if the result of a subtraction is positive or zero as the result of an inline barrel shifter operation in a move or l...

Page 627: ...encoding depending on the operands and destination register specified For some of these instructions you can force a specific instruction size by using an instruction width suffix The W suffix forces...

Page 628: ...D R A UM10360_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 628 of 808 NXP Semiconductors UM10360 Chapter 34 Appendix Cortex M3 User Guide 2 3 8 1 Example Instruction width sel...

Page 629: ...ection 34 2 4 9 LDM mode Load Multiple registers Section 34 2 4 6 LDR type Load Register using immediate offset Section 34 2 4 2 LDR type Load Register using register offset Section 34 2 4 3 LDR type...

Page 630: ...determines the address by adding an immediate value to the PC and writes the result to the destination register ADR produces position independent code because the address is PC relative If you use AD...

Page 631: ...pe is one of B unsigned byte zero extend to 32 bits on loads SB signed byte sign extend to 32 bits LDR only H unsigned halfword zero extend to 32 bits on loads SH signed halfword sign extend to 32 bit...

Page 632: ...s can either be signed or unsigned See Section 34 2 3 5 Address alignment Table 34 589 shows the ranges of offset for immediate pre indexed and post indexed forms 2 4 2 3 Restrictions For load instruc...

Page 633: ...Loads R8 from the address in R10 LDRNE R2 R5 960 Loads conditionally R2 from a word 960 bytes above the address in R5 and increments R5 by 960 STR R2 R9 const struc const struc is an expression evalua...

Page 634: ...condition code see Section 34 2 3 7 Conditional execution Rt is the register to load or store Rn is the register on which the memory address is based Rm is a register containing a value to be used as...

Page 635: ...e loaded value must be 1 for correct execution and a branch occurs to this halfword aligned address if the instruction is conditional it must be the last instruction in the IT block 2 4 3 4 Condition...

Page 636: ...ed halfword sign extend to 32 bits LDR only omit for word cond is an optional condition code see Section 34 2 3 7 Conditional execution Rt is the register to load or store Rn is the register on which...

Page 637: ...UM10360_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 637 of 808 NXP Semiconductors UM10360 Chapter 34 Appendix Cortex M3 User Guide 2 4 4 5 Examples STRBTEQ R4 R7 Conditionall...

Page 638: ...second register to load or store label is a PC relative expression See Section 34 2 3 6 PC relative expressions 2 4 5 2 Operation LDR loads a register with a value from a PC relative memory address T...

Page 639: ...Appendix Cortex M3 User Guide bit 0 of the loaded value must be 1 for correct execution and a branch occurs to this halfword aligned address if the instruction is conditional it must be the last instr...

Page 640: ...contain register ranges It must be comma separated if it contains more than one register or register range see Section 34 2 4 6 5 LDM and LDMFD are synonyms for LDMIA LDMFD refers to its use for popp...

Page 641: ...ed the value of Rn 4 n 1 is written back to Rn The PUSH and POP instructions can be expressed in this form See Section 34 2 4 7 for details 2 4 6 3 Restrictions In these instructions Rn must not be PC...

Page 642: ...he SP PUSH and POP are the preferred mnemonics in these cases 2 4 7 2 Operation PUSH stores registers on the stack in order of decreasing the register numbers with the highest numbered register using...

Page 643: ...respectively to a memory address The address used in any Store Exclusive instruction must be the same as the address in the most recently executed Load exclusive instruction The value stored by the S...

Page 644: ...x M3 User Guide do not use PC do not use SP for Rd and Rt for STREX Rd must be different from both Rt and Rn the value of offset must be a multiple of four in the range 0 1020 2 4 8 4 Condition flags...

Page 645: ...e cond is an optional condition code see Section 34 2 3 7 Conditional execution 2 4 9 2 Operation Use CLREX to make the next STREX STREXB or STREXH instruction write 1 to its destination register and...

Page 646: ...eading zeros Section 34 2 5 4 CMN Compare Negative Section 34 2 5 5 CMP Compare Section 34 2 5 5 EOR Exclusive OR Section 34 2 5 2 LSL Logical Shift Left Section 34 2 5 3 LSR Logical Shift Right Secti...

Page 647: ...tion register is Rn Rn is the register holding the first operand Operand2 is a flexible second operand See Section 34 2 3 3 for details of the options imm12 is any value in the range 0 4095 2 5 1 2 Op...

Page 648: ...the address of an instruction you have to adjust the constant based on the value of the PC ARM recommends that you use the ADR instruction instead of ADD or SUB with Rn equal to the PC because your a...

Page 649: ...D R A F T D R A F T D R A UM10360_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 649 of 808 NXP Semiconductors UM10360 Chapter 34 Appendix Cortex M3 User Guide 96 bit subtraction...

Page 650: ...optional condition code see Section 34 2 3 7 Conditional execution Rd is the destination register Rn is the register holding the first operand Operand2 is a flexible second operand See Section 34 2 3...

Page 651: ...R A F T D D R A F T D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10360_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 651 of 808 NXP Semiconductors UM10360 Chapter 3...

Page 652: ...register Rm is the register holding the shift length to apply to the value in Rm Only the least significant byte is used and can be in the range 0 to 255 Rs s the register holding the shift length to...

Page 653: ...ndix Cortex M3 User Guide 2 5 3 4 Condition flags If S is specified these instructions update the N and Z flags according to the result the C flag is updated to the last bit shifted out except when th...

Page 654: ...5 4 CLZ Count Leading Zeros 2 5 4 1 Syntax CLZ cond Rd Rm where cond is an optional condition code see Section 34 2 3 7 Rd is the destination register Rm is the operand register 2 5 4 2 Operation The...

Page 655: ...e second operand See Flexible second operand on page 3 10for details of the options 2 5 5 2 Operation These instructions compare the value in a register with Operand2 They update the condition flags o...

Page 656: ...nto Rd When Operand2 in a MOV instruction is a register with a shift other than LSL 0 the preferred syntax is the corresponding shift instruction ASR S cond Rd Rm n is the preferred syntax for MOV S c...

Page 657: ...curs to the address created by forcing bit 0 of that value to 0 Remark Though it is possible to use MOV as a branch instruction ARM strongly recommends the use of a BX or BLX instruction to branch for...

Page 658: ...imm16 where cond is an optional condition code see Section 34 2 3 7 Rd is the destination register imm16 is a 16 bit immediate constant 2 5 7 2 Operation MOVT writes a 16 bit immediate value imm16 to...

Page 659: ...tination register Rn is the register holding the operand 2 5 8 2 Operation Use these instructions to change endianness of data REV converts 32 bit big endian data into little endian data or 32 bit lit...

Page 660: ...of Operand2 This is the same as the ANDS instruction except that it discards the result To test whether a bit of Rn is 0 or 1 use the TST instruction with an Operand2 constant that has that bit set t...

Page 661: ...y and divide instructions Table 592 Multiply and divide instructions Mnemonic Brief description See MLA Multiply with Accumulate 32 bit result Section 34 2 6 1 MLS Multiply and Subtract 32 bit result...

Page 662: ...If Rd is omitted the destination register is Rn Rn Rm are registers holding the values to be multiplied Ra is a register holding the value to be added or subtracted from 2 6 1 2 Operation The MUL ins...

Page 663: ...B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 663 of 808 NXP Semiconductors UM10360 Chapter 34 Appendix Cortex M3 User Guide 2 6 1 5 Examples MUL R10 R2 R5 Multiply R10 R2 x R5 MLA R1...

Page 664: ...instruction interprets the values from Rn and Rm as unsigned integers It multiplies these integers and places the least significant 32 bits of the result in RdLo and the most significant 32 bits of th...

Page 665: ...D R A F T D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10360_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 665 of 808 NXP Semiconductors UM10360 Chapter 34 Appendix...

Page 666: ...on 34 2 3 7 Conditional execution Rd is the destination register If Rd is omitted the destination register is Rn Rn is the register holding the value to be divided Rm is a register holding the divisor...

Page 667: ...turate to n ranges from 1 to 32 for SSAT n ranges from 0 to 31 for USAT Rm is the register containing the value to saturate shift s is an optional shift applied to Rm before saturating It must be one...

Page 668: ...tion If saturation occurs the instruction sets the Q flag to 1 in the APSR Otherwise it leaves the Q flag unchanged To clear the Q flag to 0 you must use the MSR instruction see Section 34 2 10 7 To r...

Page 669: ...2 8 Bitfield instructions Table 34 593 shows the instructions that operate on adjacent sets of bits in registers or bitfields Table 593 Packing and unpacking instructions Mnemonic Brief description S...

Page 670: ...ister lsb is the position of the least significant bit of the bitfield lsb must be in the range 0 to 31 width is the width of the bitfield and must be in the range 1 to 32 lsb 2 8 1 2 Operation BFC cl...

Page 671: ...source register lsb is the position of the least significant bit of the bitfield lsb must be in the range 0 to 31 width is the width of the bitfield and must be in the range 1 to 32 lsb 2 8 2 2 Opera...

Page 672: ...n code see Section 34 2 3 7 Conditional execution Rd is the destination register Rm is the register holding the value to extend ROR n is one of ROR 8 Value from Rm is rotated right 8 bits ROR 16 Value...

Page 673: ...V 2009 All rights reserved User manual Rev 00 06 5 June 2009 673 of 808 NXP Semiconductors UM10360 Chapter 34 Appendix Cortex M3 User Guide 2 8 3 5 Examples SXTH R4 R6 ROR 16 Rotate R6 right by 16 bi...

Page 674: ...User Guide 2 9 Branch and control instructions Table 34 594 shows the branch and control instructions Table 594 Branch and control instructions Mnemonic Brief description See B Branch Section 34 2 9 1...

Page 675: ...be 1 but the address to branch to is created by changing bit 0 to 0 2 9 1 2 Operation All these instructions cause a branch to label or to the address indicated in Rm In addition The BL and BLX instru...

Page 676: ...of these instructions is inside an IT block it must be the last instruction of the IT block Bcond is the only conditional instruction that is not required to be inside an IT block However it has a lon...

Page 677: ...anch destination 2 9 2 2 Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions CBZ Rn label does not change condition flags but...

Page 678: ...h of x y and z must be T or omitted but not E 2 9 3 2 Operation The IT instruction makes up to four following instructions conditional The conditions can be all the same or some of them can be the log...

Page 679: ...has a larger branch range if it is inside one each instruction inside the IT block must specify a condition code suffix that is either the same or logical inverse as for the other instructions in the...

Page 680: ...D D R A F T D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10360_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 680 of 808 NXP Semiconductors UM10360 Chapter 34 Append...

Page 681: ...table of single byte offsets for TBB or halfword offsets for TBH Rn provides a pointer to the table and Rm supplies an index into the table For TBB the branch offset is twice the unsigned value of the...

Page 682: ...00 06 5 June 2009 682 of 808 NXP Semiconductors UM10360 Chapter 34 Appendix Cortex M3 User Guide TBH PC R1 LSL 1 R1 is the index PC is used as base of the branch table BranchTable_H DCI CaseA BranchTa...

Page 683: ...uctions Mnemonic Brief description See BKPT Breakpoint Section 34 2 10 1 CPSID Change Processor State Disable Interrupts Section 34 2 10 2 CPSIE Change Processor State Enable Interrupts Section 34 2 1...

Page 684: ...value 2 10 1 2 Operation The BKPT instruction causes the processor to enter Debug state Debug tools can use this to investigate system state when the instruction at a particular address is reached imm...

Page 685: ...PRIMASK f Set or clear FAULTMASK 2 10 2 2 Operation CPS changes the PRIMASK and FAULTMASK special register values See Section 35 1 1 3 6 Exception mask registers for more information about these regis...

Page 686: ...rrier 2 10 3 1 Syntax DMB cond where cond is an optional condition code see Section 34 2 3 7 Conditional execution 2 10 3 2 Operation DMB acts as a data memory barrier It ensures that all explicit mem...

Page 687: ...Guide 2 10 4 DSB Data Synchronization Barrier 2 10 4 1 Syntax DSB cond where cond is an optional condition code see Section 34 2 3 7 Conditional execution 2 10 4 2 Operation DSB acts as a special dat...

Page 688: ...3 User Guide 2 10 5 ISB Instruction Synchronization Barrier 2 10 5 1 Syntax ISB cond where cond is an optional condition code see Section 34 2 3 7 Conditional execution 2 10 5 2 Operation ISB acts as...

Page 689: ...R EAPSR PSR MSP PSP PRIMASK BASEPRI BASEPRI_MAX FAULTMASK or CONTROL 2 10 6 2 Operation Use MRS in combination with MSR as part of a read modify write sequence for updating a PSR for example to clear...

Page 690: ...EAPSR PSR MSP PSP PRIMASK BASEPRI BASEPRI_MAX FAULTMASK or CONTROL 2 10 7 2 Operation The register access operation in MSR depends on the privilege level Unprivileged software can only access the APS...

Page 691: ...pendix Cortex M3 User Guide 2 10 8 NOP No Operation 2 10 8 1 Syntax NOP cond where cond is an optional condition code see Section 34 2 3 7 Conditional execution 2 10 8 2 Operation NOP does nothing NOP...

Page 692: ...ors UM10360 Chapter 34 Appendix Cortex M3 User Guide 2 10 9 SEV Send Event 2 10 9 1 Syntax SEV cond where cond is an optional condition code see Section 34 2 3 7 Conditional execution 2 10 9 2 Operati...

Page 693: ...0 10 1 Syntax SVC cond imm where cond is an optional condition code see Section 34 2 3 7 Conditional execution imm is an expression evaluating to an integer in the range 0 255 8 bit value 2 10 10 2 Op...

Page 694: ...2 Operation WFE is a hint instruction If the event register is 0 WFE suspends execution until one of the following events occurs an exception unless masked by the exception mask registers or the curre...

Page 695: ...ctors UM10360 Chapter 34 Appendix Cortex M3 User Guide 2 10 12 WFI Wait for Interrupt 2 10 12 1 Syntax WFI cond where cond is an optional condition code see Section 34 2 3 7 Conditional execution 2 10...

Page 696: ...C or system control block might have restricted access to memory or peripherals Unprivileged software executes at the unprivileged level Privileged The software can use all the instructions and has ac...

Page 697: ...ivileged 1 Main stack or process stack 1 Handler Exception handlers Always privileged Main stack 63 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 RZ UHJLVWHUV LJK UHJLVWHUV 063 363 365 35 0 6 8 70 6 6 35 21752...

Page 698: ...1 Process Stack Pointer PSP 3 1 3 3 Link Register The Link Register LR is register R14 It stores the return information for subroutines function calls and exceptions On reset the processor loads the...

Page 699: ...e MSR instruction The PSR combinations and attributes are 1 The processor ignores writes to the IPSR bits 2 Reads of the EPSR bits return zero and the processor ignores writes to the these bits See th...

Page 700: ...tion 31 N Negative or less than flag 0 operation result was positive zero greater than or equal 1 operation result was negative or less than 30 Z Zero flag 0 operation result was not zero 1 operation...

Page 701: ...gister summary in Table 34 598 for the EPSR attributes The bit assignments are Table 601 IPSR bit assignments Bits Name Function 31 9 Reserved 8 0 ISR_NUMBER This is the number of the current exceptio...

Page 702: ...instruction in the block is conditional The conditions for the instructions are either all the same or some can be the inverse of others See Section 36 1 9 3 IT for more information 3 1 3 6 Exception...

Page 703: ...s attributes The bit assignments are shown in Table 34 606 Handler mode always uses the MSP so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Han...

Page 704: ...34 3 2 1 for more information 3 1 6 The Cortex Microcontroller Software Interface Standard For a Cortex M3 microcontroller system the Cortex Microcontroller Software Interface Standard CMSIS defines a...

Page 705: ...D R A UM10360_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 705 of 808 NXP Semiconductors UM10360 Chapter 34 Appendix Cortex M3 User Guide The following sections give more infor...

Page 706: ...is The regions for SRAM and peripherals include bit band regions Bit banding provides atomic operations to bit data see Section 34 3 2 5 The processor reserves regions of the Private peripheral bus P...

Page 707: ...e If multiple bus masters can access a non shareable memory region software must ensure data coherency between the bus masters Execute Never XN Means the processor prevents instruction accesses Any at...

Page 708: ...ry accesses to improve efficiency providing this does not affect the behavior of the instruction sequence the processor has multiple bus interfaces memory or devices in the memory map have different w...

Page 709: ...configuration code is entered using exception mechanisms then an ISB instruction is not required Vector table If the program changes an entry in the vector table and then enables the corresponding exc...

Page 710: ...s of the alias region Byte_offset is the number of the byte in the bit band region that contains the targeted bit Bit_number is the bit position 0 7 of the targeted bit Figure 34 143 shows examples of...

Page 711: ...on Writing to a word in the alias region updates a single bit in the bit band region Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bi...

Page 712: ...rimitives The Cortex M3 instruction set includes pairs of synchronization primitives These provide a non blocking mechanism that a thread or process can use to obtain exclusive access to a memory loca...

Page 713: ...ddress 3 If the returned status bit from step 2 indicates that the Store Exclusive succeeded then the software has claimed the semaphore However if the Store Exclusive failed another process might hav...

Page 714: ...A F T D R A F T D R A F T D R A F T D D R A F T D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10360_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 714 of 808 NXP Semi...

Page 715: ...eption is being serviced by the processor and there is a pending exception from the same source 3 3 2 Exception types The exception types are Reset Reset is invoked on power up or a warm reset The exc...

Page 716: ...exception return The following can cause a usage fault when the core is configured to report them an unaligned address on word and halfword memory access division by zero SVCall A supervisor call SVC...

Page 717: ...ty see Section 37 1 3 10 System Handler Control and State Register Section 37 1 2 3 Interrupt Clear enable Registers For more information about hard faults memory management faults bus faults and usag...

Page 718: ...Privileged software can write to the VTOR to relocate the vector table start address to a different memory location in the range 0x00000080 to 0x3FFFFF80 see Section 37 1 3 5 Vector Table Offset Regis...

Page 719: ...wever the status of the new interrupt changes to pending 3 3 6 Interrupt priority grouping To increase priority control in systems with interrupts the NVIC supports priority grouping This divides each...

Page 720: ...ed The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor On return from the except...

Page 721: ...ponding pending interrupt to active If another higher priority exception occurs during exception entry the processor starts executing the exception handler for this exception and does not change the p...

Page 722: ...009 All rights reserved User manual Rev 00 06 5 June 2009 722 of 808 NXP Semiconductors UM10360 Chapter 34 Appendix Cortex M3 User Guide b1001 Return to Thread mode Exception return gets state from MS...

Page 723: ...rred See Section 37 1 3 11 Configurable Fault Status Register for more information about the fault status registers 1 Occurs on an access to an XN region even if the MPU is disabled 2 Attempting to us...

Page 724: ...rity as the fault it is servicing This is because the handler for the new fault cannot preempt the currently executing fault handler An exception handler causes a fault for which the priority is the s...

Page 725: ...725 of 808 NXP Semiconductors UM10360 Chapter 34 Appendix Cortex M3 User Guide 3 4 4 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers Whe...

Page 726: ...an generate spurious wakeup events for example a debug operation wakes up the processor Therefore software must be able to put the processor back into sleep mode after such an event A program might ha...

Page 727: ...FAULTMASK see Section 34 3 1 3 6 3 5 2 2 Wakeup from WFE The processor wakes up if it detects an exception with sufficient priority to cause exception entry In addition if the SEVONPEND bit in the SC...

Page 728: ...60_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 728 of 808 NXP Semiconductors UM10360 Chapter 34 Appendix Cortex M3 User Guide 3 5 4 Power management programming hints ANSI C c...

Page 729: ...ilege level required to access the register as follows Privileged Only privileged software can access the register Unprivileged Both unprivileged and privileged software can access the register Table...

Page 730: ...ICER 1 corresponds to the ICER1 register 4 2 1 The CMSIS mapping of the Cortex M3 NVIC registers To improve software efficiency the CMSIS simplifies the NVIC register presentation In the CMSIS the Se...

Page 731: ...616 for the register attributes Table 34 617 for which interrupts are controlled by each register The bit assignments are shown in Table 34 618 If a pending interrupt is enabled the NVIC activates the...

Page 732: ...4 620 Remark Writing 1 to the ISPR bit corresponding to an interrupt that is pending has no effect a disabled interrupt sets the state of that interrupt to pending 4 2 5 Interrupt Clear pending Regist...

Page 733: ...shown in Table 34 622 A bit reads as one if the status of the corresponding interrupt is active or active and pending 4 2 7 Interrupt Priority Registers The IPR0 IPR27 registers provide a 5 bit prior...

Page 734: ...ark Only privileged software can enable unprivileged access to the STIR The bit assignments are shown in Table 34 624 4 2 9 Level sensitive and pulse interrupts The processor supports both level sensi...

Page 735: ...cessor returns from the ISR the NVIC samples the interrupt signal If the signal is asserted the state of the interrupt changes to pending which might cause the processor to immediately re enter the IS...

Page 736: ...ovides a number of functions for NVIC control including For more information about these functions see the CMSIS documentation Table 625 CMSIS functions for NVIC control CMSIS interrupt control functi...

Page 737: ...p interruption of multi cycle instructions See the register summary in Table 34 626 for the ACTLR attributes The bit assignments are shown in Table 34 627 Table 626 Summary of the system control block...

Page 738: ...pending and clear pending bits for the PendSV and SysTick exceptions indicates the exception number of the exception being processed Table 627 ACTLR bit assignments Bits Name Function 31 3 Reserved 2...

Page 739: ...ate to pending Read 0 NMI exception is not pending 1 NMI exception is pending Because NMI is the highest priority exception normally the processor enter the NMI exception handler as soon as it registe...

Page 740: ...24 Reserved 23 Reserved for Debug use RO This bit is reserved for Debug use and reads as zero when the processor is not in Debug 22 ISRPENDING RO Interrupt pending flag excluding NMI and Faults 0 inte...

Page 741: ...e the register summary in Table 34 626 and Table 34 631 for its attributes To write to this register you must write 0x5VA to the VECTKEY field otherwise the processor ignores the write The bit assignm...

Page 742: ...s of entry to and exit from low power state See the register summary in Table 34 626 for its attributes The bit assignments are shown in Table 34 633 2 SYSRESETREQ WO System reset request 0 no system...

Page 743: ...signments Bits Name Function 31 5 Reserved 4 SEVONPEND Send Event on Pending bit 0 only enabled interrupts or events can wakeup the processor disabled interrupts are excluded 1 enabled events and all...

Page 744: ...the hard fault NMI and FAULTMASK escalated handlers 0 data bus faults caused by load and store instructions cause a lock up 1 handlers running at priority 1 and 2 ignore data bus faults caused by loa...

Page 745: ...s and indicates the pending status of the bus fault memory management fault and SVC exceptions the active status of the system handlers See the register summary in Table 34 626 for the SHCSR attribute...

Page 746: ...software that writes to this register retains and subsequently restores the current active status After you have enabled the system handlers if you have to change the value of a bit in this register y...

Page 747: ...0xE000ED28 access the BFSR with a byte access to 0xE000ED29 access the UFSR with a halfword access to 0xE000ED2A 4 3 11 1 Memory Management Fault Status Register The flags in the MMFSR indicate the ca...

Page 748: ...hat does not permit the operation When this bit is 1 the PC value stacked for the exception return points to the faulting instruction The processor has loaded the MMAR with the address of the attempte...

Page 749: ...t address to the BFAR 2 IMPRECISERR Imprecise data bus error 0 no imprecise data bus error 1 a data bus error has occurred but the return address in the stack frame is not related to the instruction t...

Page 750: ...in the CCR to 1 see Table 34 634 Unaligned LDM STM LDRD and STRD instructions always fault irrespective of the setting of UNALIGN_TRP 7 4 Reserved 3 NOCP No coprocessor usage fault The processor does...

Page 751: ...the fault address can be any address in the range of the requested access size Flags in the MMFSR indicate the cause of the fault and whether the value in the MMFAR is valid See Table 34 640 4 3 14 Bu...

Page 752: ...ystem control block registers except for the CFSR and SHPR1 SHPR3 it must use aligned word accesses for the CFSR and SHPR1 SHPR3 it can use byte or aligned halfword or word accesses The processor does...

Page 753: ...for its attributes The bit assignments are shown in Table 34 647 When ENABLE is set to 1 the counter loads the RELOAD value from the LOAD register and then counts down On reaching 0 it sets the COUNT...

Page 754: ...LOAD to 99 To deliver a single SysTick interrupt after a delay of N processor clock cycles use a RELOAD of value N For example if a SysTick interrupt is required after 400 clock pulses set RELOAD to 4...

Page 755: ...the frequency of the processor clock or external clock 4 4 5 SysTick design hints and tips The SysTick counter runs on the processor clock If this clock signal is stopped for low power mode while the...

Page 756: ...ground region has the same memory access attributes as the default memory map but is accessible from privileged software only The Cortex M3 MPU memory map is unified This means instruction accesses an...

Page 757: ...ingle processor uses Table 651 Memory attributes summary Memory type Shareability Other attributes Description Table 652 MPU registers summary Address Name Type Required privilege Reset value Descript...

Page 758: ...emory maps 0 unified Table 653 TYPE register bit assignments Bits Name Function Table 654 MPU CTRL register bit assignments Bits Name Function 31 3 Reserved 2 PRIVDEFENA Enables privileged software ac...

Page 759: ...enabled accesses to the System Control Space and vector table are always permitted Other areas are accessible based on regions and whether PRIVDEFENA is set to 1 Unless HFNMIENA is set to 1 the MPU i...

Page 760: ...nes the region size and memory attributes of the MPU region specified by the RNR and enables that region and any subregions See the register summary in Table 34 652 for its attributes RASR is accessib...

Page 761: ...unction 31 29 Reserved 28 XN Instruction access disable bit 0 instruction fetches enabled 1 instruction fetches disabled 27 Reserved 26 24 AP Access permission field see Table 34 661 23 22 Reserved 21...

Page 762: ...gs with a TEX value is in the range 4 7 Table 34 661 shows the AP encodings that define the access permissions for privileged and unprivileged software Table 659 TEX C B and S encoding TEX C B S Memor...

Page 763: ...four regions simultaneously using an STM instruction 4 5 8 1 Updating an MPU region using separate words Simple code to configure one region R1 region number R2 size enable R3 attributes R4 address L...

Page 764: ...ntering an exception handler or is followed by an exception return because the exception entry and exception return mechanism cause memory barrier behavior Software does not need any memory barrier in...

Page 765: ...ion Attribute Size and Enable Use an STM instruction to optimize this R1 address and region number in one R2 size and attributes in one LDR R0 MPU_RBAR 0xE000ED9C MPU Region Base register STM R0 R1 R2...

Page 766: ...the new MPU setup 4 5 9 1 MPU configuration for a microcontroller Usually a microcontroller system has only a single processor and no caches In such a system program the MPU as follows In most microco...

Page 767: ...register Big endian BE Byte ordering scheme in which bytes of decreasing significance in a data word are stored at increasing addresses in memory See also Byte invariant Endianness Little endian Big e...

Page 768: ...eight Endianness Byte ordering The scheme that determines the order that successive bytes of a data word are stored in memory An aspect of the system s memory mapping See also Little endian and Big en...

Page 769: ...ed address is the least significant byte or halfword within the word at that address a byte at a halfword aligned address is the least significant byte within the halfword at that address See also Big...

Page 770: ...ot divisible by four Unpredictable UNP You cannot rely on the behavior Unpredictable behavior must not represent security holes Unpredictable behavior must not halt or hang the processor or any parts...

Page 771: ...Architecture APB Advanced Peripheral Bus BOD BrownOut Detection CAN Controller Area Network DAC Digital to Analog Converter DCC Debug Communication Channel DMA Direct Memory Access DSP Digital Signal...

Page 772: ...document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication he...

Page 773: ...R A F T D R A F T D R A F T D R A F T D D R A F T D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10360_0 NXP B V 2009 All rights reserved User manual Rev 00 06 5 June 2009 773 of 808 conti...

Page 774: ...ltiplier Values for use with a Low Frequency Clock Input 37 Table 27 Potential values for PLL example 39 Table 28 PLL1 registers 41 Table 29 PLL1 Control register PLL1CON address 0x400F C0A0 bit descr...

Page 775: ...80 bit description 94 Table 82 Fast GPIO port Direction control byte and half word accessible register description 95 Table 83 Fast GPIO port output Set register FIO0SET to FIO7SET addresses 0x2009 C0...

Page 776: ...0C bit description 130 Table 130 Receive Number of Descriptors register RxDescriptor address 0x5000 0110 bit description 130 Table 131 Receive Produce Index register RxProduceIndex address 0x5000 0114...

Page 777: ...St address 0x5000 C230 bit allocation 195 Table 180 USB Endpoint Interrupt Status register USBEpIntSt address 0x5000 C230 bit description 196 Table 181 USB Endpoint Interrupt Enable register USBEpIntE...

Page 778: ...ster bit description 218 Table 224 Get Error Code Register bit description 220 Table 225 Read Error Status Register bit description 220 Table 226 Select Endpoint Register bit description 221 Table 227...

Page 779: ...ption 294 Table 271 UART1 Divisor Latch LSB Register U1DLL address 0x4001 0000 when DLAB 1 bit description 295 Table 272 UART1 Divisor Latch MSB Register U1DLM address 0x4001 0004 when DLAB 1 bit desc...

Page 780: ...address 0x4004 80 3C 4C 5C bit description 344 Table 315 CAN Sleep Clear register CANSLEEPCLR address 0x400F C110 bit description 344 Table 316 CAN Wake up Flags register CANWAKEFLAGS address 0x400F C...

Page 781: ...I2C register map 413 Table 364 I2C Control Set register I2CONSET I2C0 I2C0CONSET address 0x4001 C000 I2C1 I2C1CONSET address 0x4005 C000 I2C2 I2C2CONSET address 0x400A 0000 bit description 415 Table 3...

Page 782: ...ister T 0 1 2 3 CTCR addresses 0x4000 4070 0x4000 8070 0x4009 0070 0x4009 4070 bit description 467 Table 410 Match Control Register T 0 1 2 3 MCR addresses 0x4000 4014 0x4000 8014 0x4009 0014 0x4009 4...

Page 783: ...Table 460 MCPWM Capture clear address CAP_CLR 0x400B 8074 bit description 509 Table 461 Encoder states 518 Table 462 Encoder state transitions 1 518 Table 463 Encoder direction 519 Table 464 QEI pin d...

Page 784: ...gister AD0GDR address 0x4003 4004 bit description 552 Table 515 A D Status register AD0INTEN address 0x4003 400C bit description 553 Table 516 A D Data Registers AD0DR0 to AD0DR7 0x4003 4010 to 0x4003...

Page 785: ...611 Table 584 Cortex M3 instructions 616 Table 585 CMSIS intrinsic functions to generate some Cortex M3 instructions 619 Table 586 CMSIS intrinsic functions to access the special registers 619 Table...

Page 786: ...assignments 750 Table 643 HFSR bit assignments 751 Table 644 MMFAR bit assignments 751 Table 645 BFAR bit assignments 752 Table 646 System timer registers summary 753 Table 647 SysTick CTRL register...

Page 787: ...ith software stack 259 Fig 38 Hardware support for B device switching from peripheral state to host state 260 Fig 39 State transitions implemented in software during B device switching from peripheral...

Page 788: ...nd WS 458 Fig 102 Typical transmitter slave mode 458 Fig 103 Transmitter slave mode sharing the receiver reference clock 458 Fig 104 4 wire transmitter slave mode sharing the receiver bit clock and WS...

Page 789: ...20 6 1 Register description 20 6 2 External Interrupt flag register EXTINT 0x400F C140 20 6 3 External Interrupt Mode register EXTMODE 0x400F C148 21 6 4 External Interrupt Polarity register EXTPOLAR...

Page 790: ...from Reduced Power Modes 54 8 9 Power Control for Peripherals register PCONP 0x400F C0C4 54 8 10 Power control usage notes 56 8 11 Power domains 56 9 Wake up timer 56 10 External clock output pin 57 1...

Page 791: ...er FIOxCLR FIO0CLR to FIO7CLR 0x2009 C01C to 0x2009 C09C 97 5 4 GPIO port Pin value register FIOxPIN FIO0PIN to FIO7PIN 0x2009 C014 to 0x2009 C094 98 5 5 Fast GPIO port Mask register FIOxMASK FIO0MASK...

Page 792: ...ProduceIndex 0x5000 0114 130 12 7 Receive Consume Index Register RxConsumeIndex 0x5000 0118 131 12 8 Transmit Descriptor Base Address Register TxDescriptor 0x5000 011C 131 12 9 Transmit Status Base Ad...

Page 793: ...3 Power management support 188 9 4 Remote wake up 189 10 Register description 189 10 1 Clock control registers 190 10 1 1 USB Clock Control register USBClkCtrl 0x5000 CFF4 190 10 1 2 USB Clock Status...

Page 794: ...r 0x5000 C2BC 211 10 7 18 USB System Error Interrupt Set register USBSysErrIntSet 0x5000 C2C0 212 11 Interrupt handling 212 12 Serial interface engine command description 215 12 1 Set Address Command...

Page 795: ...Register Definitions 244 Chapter 13 LPC17xx USB OTG controller 1 How to read this chapter 245 2 Basic configuration 245 3 Introduction 245 4 Features 245 5 Architecture 246 6 Modes of operation 246 7...

Page 796: ...0x4009 801C U3SCR 0x4009 C01C 280 4 10 UARTn Auto baud Control Register U0ACR 0x4000 C020 U2ACR 0x4009 8020 U3ACR 0x4009 C020 280 14 4 10 1 Auto baud 281 14 4 10 2 Auto baud modes 282 4 11 UARTn IrDA...

Page 797: ...4004 8008 328 7 4 CAN Interrupt and Capture Register CAN1ICR 0x4004 400C CAN2ICR 0x4004 800C 330 7 5 CAN Interrupt Enable Register CAN1IER 0x4004 4010 CAN2IER 0x4004 8010 334 7 6 CAN Bus Timing Regist...

Page 798: ...its IntPnd 63 to 0 364 16 2 4 Clearing the interrupt pending bits IntPnd 63 to 0 364 16 2 5 Setting the message lost bit of a FullCAN message object MsgLost 63 to 0 364 16 2 6 Clearing the message los...

Page 799: ...0 6 8 SSPn Masked Interrupt Status Register SSP0MIS 0x4008 801C SSP1MIS 0x4003 001C 400 6 9 SSPn Interrupt Clear Register SSP0ICR 0x4008 8020 SSP1ICR 0x4003 0020 401 6 10 SSPn DMA Control Register SSP...

Page 800: ...435 9 6 1 Simultaneous repeated START conditions from two masters 435 9 6 2 Data transfer after loss of arbitration 435 9 6 3 Forced access to the I2C bus 435 9 6 4 I2C bus obstructed by a LOW level...

Page 801: ...Interrupt Register T 0 1 2 3 IR 0x4000 4000 0x4000 8000 0x4009 0000 0x4009 4000 466 6 2 Timer Control Register T 0 1 2 3 CR 0x4000 4004 0x4000 8004 0x4009 0004 0x4009 4004 466 6 3 Count Control Regist...

Page 802: ...odules for MCPWM use 496 6 General Operation 496 7 Register description 497 7 1 MCPWM Control register 498 7 1 1 MCPWM Control read address MCCON 0x400B 8000 498 7 1 2 MCPWM Control set address MCCON_...

Page 803: ...ter QEISTAT 0x400B C004 522 6 3 Position index and timer registers 522 6 3 1 QEI Position register QEIPOS 0x400B C00C 522 6 3 2 QEI Maximum Position register QEIMAXPOS 0x400B C010 523 6 3 3 QEI Positi...

Page 804: ...1 Watchdog Mode register WDMOD 0x4000 0000 544 4 2 Watchdog Timer Constant register WDTC 0x4000 0004 545 4 3 Watchdog Feed register WDFEED 0x4000 0008 546 4 4 Watchdog Timer Value register WDTV 0x4000...

Page 805: ...ftware Last Burst Request register DMACSoftLBReq 0x5000 4028 573 5 12 DMA Software Last Single Request register DMACSoftLSReq 0x5000 402C 573 5 13 DMA Configuration register DMACConfig 0x5000 4030 573...

Page 806: ...ad device serial number 608 8 8 Compare address1 address2 no of bytes 608 8 9 Re invoke ISP 608 8 10 IAP Status Codes 609 9 JTAG flash programming interface 609 Chapter 33 LPC17xx JTAG Serial Wire Deb...

Page 807: ...3 2 Exception types 715 3 3 3 Exception handlers 717 3 3 4 Vector table 718 3 3 5 Exception priorities 718 3 3 6 Interrupt priority grouping 719 3 3 7 Exception entry and return 719 3 4 Fault handlin...

Page 808: ...information 808 4 4 1 SysTick Control and Status Register 753 4 4 2 SysTick Reload Value Register 754 4 4 3 SysTick Current Value Register 754 4 4 4 SysTick Calibration Value Register 754 4 4 5 SysTi...

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