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UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
45 of 808
NXP Semiconductors
UM10360
Chapter 4: LPC17xx Clocking and power control
6.6 PLL1 Feed register (PLL1FEED - 0x400F C0AC)
A correct feed sequence must be written to the PLL1FEED register in order for changes to
the PLL1CON and PLL1CFG registers to take effect. The feed sequence is:
1. Write the value 0xAA to PLL1FEED.
2. Write the value 0x55 to PLL1FEED.
The two writes must be in the correct sequence, and there must be no other register
access in the same address space (0x400F C000 to 0x400F FFFF) between them.
Because of this, it may be necessary to disable interrupts for the duration of the PLL feed
operation, if there is a possibility that an interrupt service routine could write to another
register in that space. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLL1CON or PLL1CFG register will
not become effective.
6.7 PLL1 and Power-down mode
Power-down mode automatically turns off and disconnects activated PLL(s). Wake-up
from Power-down mode does not automatically restore PLL settings, this must be done in
software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due to
the wake-up. It is important not to attempt to restart a PLL by simply feeding it when
execution resumes after a wake-up from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.
If activity on the USB data lines is not selected to wake the microcontroller from
Power-down mode (see
for details of wake up from reduced modes), both
the Main PLL (PLL0) and the USB PLL (PLL1) will be automatically be turned off and
disconnected when Power-down mode is invoked, as described above. However, if the
USB activity interrupt is enabled and USB_NEED_CLK = 1 (see
for a
description of USB_NEED_CLK), it is not possible to go into Power-down mode and any
attempt to set the PD bit will fail, leaving the PLLs in the current state.
6.8 PLL1 frequency calculation
The PLL1 equations use the following parameters:
The PLL1 output frequency (when the PLL is both active and connected) is given by:
Table 33.
PLL1 Feed register (PLL1FEED - address 0x400F C0AC) bit description
Bit
Symbol
Description
Reset
value
7:0
PLL1FEED The PLL1 feed sequence must be written to this register in order for
PLL1 configuration and control register changes to take effect.
0x00
Table 34.
Elements determining PLL frequency
Element
Description
F
OSC
the frequency from the crystal oscillator
F
CCO
the frequency of the PLL1 current controlled oscillator
USBCLK
the PLL1 output frequency (48 MHz for USB)
M
PLL1 Multiplier value from the MSEL1 bits in the PLL1CFG register
P
PLL1 Divider value from the PSEL1 bits in the PLL1CFG register