NXP Semiconductors LPC1751, User Manual, Page: 737 / 808

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UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 737 of 808
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
4.3 System control block
The System control block (SCB) provides system implementation information, and
system control. This includes configuration, control, and reporting of the system
exceptions. The system control block registers are:
[1] See the register description for more information.
[2] A subregister of the CFSR.
4.3.1 The CMSIS mapping of the Cortex-M3 SCB registers
To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the
CMSIS, the byte array
SHP[0]
to
SHP[12]
corresponds to the registers SHPR1-SHPR3.
4.3.2 Auxiliary Control Register
The ACTLR provides disable bits for the following processor functions:
•
IT folding
•
write buffer use for accesses to the default memory map
•
interruption of multi-cycle instructions.
See the register summary in Table 34–626 for the ACTLR attributes. The bit assignments
are shown in Table 34–627 .
Table 626. Summary of the system control block registers
Address Name Type Required
privilege Reset
value Description
0xE000E008
ACTLR RW Privileged
0x00000000
Table 34–627
0xE000ED00
CPUID RO Privileged
0x412FC230
Table 34–628
0xE000ED04
ICSR RW
[1]
Privileged
0x00000000
Table 34–629
0xE000ED08
VTOR RW Privileged
0x00000000
Table 34–630
0xE000ED0C
AIRCR RW
[1]
Privileged
0xFA050000
Table 34–631
0xE000ED10
SCR RW Privileged
0x00000000
Table 34–633
0xE000ED14
CCR RW Privileged
0x00000200
Table 34–634
0xE000ED18
SHPR1 RW Privileged
0x00000000
Table 34–636
0xE000ED1C
SHPR2 RW Privileged
0x00000000
Table 34–637
0xE000ED20
SHPR3 RW Privileged
0x00000000
Table 34–638
0xE000ED24
SHCRS RW Privileged
0x00000000
Table 34–639
0xE000ED28
CFSR RW Privileged
0x00000000
Section 34–4.3.11
0xE000ED28
MMSR
[2]
RW Privileged
0x00
Table 34–640
0xE000ED29
BFSR
[2]
RW Privileged
0x00
Table 34–641
0xE000ED2A
UFSR
[2]
RW Privileged
0x0000
Table 34–642
0xE000ED2C
HFSR RW Privileged
0x00000000
Table 34–643
0xE000ED34
MMFAR RW Privileged Undefined Table 34–644
0xE000ED38
BFAR RW Privileged Undefined Table 34–645