NXP Semiconductors LPC1751, User Manual, Page: 451 / 808

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UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 451 of 808
NXP Semiconductors
UM10360
Chapter 20: LPC17xx I2S interface
5.3 Transmit FIFO register (I2STXFIFO - 0x400A 8008)
The I2STXFIFO register provides access to the transmit FIFO. The function of bits in
I2STXFIFO are shown in
Table 20–388 .
5.4 Receive FIFO register (I2SRXFIFO - 0x400A 800C)
The I2SRXFIFO register provides access to the receive FIFO. The function of bits in
I2SRXFIFO are shown in
Table 20–389 .
5.5 Status Feedback register (I2SSTATE - 0x400A 8010)
The I2SSTATE register provides status information about the I
2
S interface. The meaning
of bits in I2SSTATE are shown in Table 20–390 .
5.6 DMA Configuration Register 1 (I2SDMA1 - 0x400A 8014)
The I2SDMA1 register controls the operation of DMA request 1. The function of bits in
I2SDMA1 are shown in
Table 20–391 . Refer to the General Purpose DMA Controller
chapter for details of DMA operation.
Table 388: Transmit FIFO register (I2STXFIFO - address 0x400A 8008) bit description
Bit Symbol Description Reset Value
31:0 I2STXFIFO 8
×
32-bit transmit FIFO. Level = 0
Table 389: Receive FIFO register (I2RXFIFO - address 0x400A 800C) bit description
Bit Symbol Description Reset Value
31:0 I2SRXFIFO 8
×
32-bit transmit FIFO. level = 0
Table 390: Status Feedback register (I2SSTATE - address 0x400A 8010) bit description
Bit Symbol Description Reset
Value
0 irq This bit reflects the presence of Receive Interrupt or
Transmit Interrupt. 0
1 dmareq1 This bit reflects the presence of Receive or Transmit DMA
Request 1. 0
2 dmareq2 This bit reflects the presence of Receive or Transmit DMA
Request 2. 0
7:3 Unused Unused. 0
12:8 rx_level Reflects the current level of the Receive FIFO. 0
15:13 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
20:16 tx_level Reflects the current level of the Transmit FIFO. 0
31:21 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA