DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
FT DRAF
D
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DRAFT
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UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
420 of 808
NXP Semiconductors
UM10360
Chapter 19: LPC17xx I2C0/1/2 interface
8.7 I
2
C Slave Address registers (I2ADR0 to 3: I
2
C0, I2C0ADR[0, 1, 2, 3]-
0x4001 C0[0C, 20, 24, 28]; I
2
C1, I2C1ADR[0, 1, 2, 3] - address
0x4005 C0[0C, 20, 24, 28]; I
2
C2, I2C2ADR[0, 1, 2, 3] - address
0x400A 00[0C, 20, 24, 28])
These registers are readable and writable and are only used when an I
2
C interface is set
to slave mode. In master mode, this register has no effect. The LSB of I2ADR is the
General Call bit. When this bit is set, the General Call address (0x00) is recognized.
If these registers contains 0x00, it will be disabled and will not acknowledge any address
on the bus. All four registers will be cleared to this disabled state on reset.
8.8 I
2
C Mask registers (I2MASK0 to 3: I
2
C0, I2C0MASK[0, 1, 2, 3] -
0x4001 C0[30, 34, 38, 3C]; I
2
C1, I2C1MASK[0, 1, 2, 3] - address
0x4005 C0[30, 34, 38, 3C]; I
2
C2, I2C2MASK[0, 1, 2, 3] - address
0x400A 00[30, 34, 38, 3C])
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to ‘1’ will cause an automatic compare on the corresponding bit of the
received address when it is compared to the I2ADRn register associated with that mask
register. In other words, bits in an I2ADRn register which are masked are not taken into
account in determining an address match.
On reset, all mask register bits are cleared to ‘0’.
The mask register has no effect on comparison to the General Call address (“0000000”).
Bits(31:8) and bit(0) of the mask registers are unused and should be written with zeroes.
When an address-match interrupt occurs, the processor will have to read the data register
(I2DAT) to determine which received address actually caused the match.
Table 370. I
2
C Slave Address registers (I2ADR0 to 3: I
2
C0, I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C,
20, 24, 28]; I
2
C1, I2C1ADR[0, 1, 2, 3] - address 0x4005 C0[0C, 20, 24, 28]; I
2
C2,
I2C2ADR[0, 1, 2, 3] - address 0x400A 00[0C, 20, 24, 28]) bit description
Bit Symbol
Description
Reset value
0
GC
General Call enable bit.
0
7:1 Address
The I
2
C device address for slave mode.
0x00
Table 371. I
2
C Mask registers (I2MASK0 to 3: I
2
C0, I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34,
38, 3C]; I
2
C1, I2C1MASK[0, 1, 2, 3] - address 0x4005 C0[30, 34, 38, 3C]; I
2
C2,
I2C2MASK[0, 1, 2, 3] - address 0x400A 00[30, 34, 38, 3C]) bit description
Bit
Symbol
Description
Reset
value
0
-
Reserved. User software should not write ones to reserved bits. This
bit reads always back as 0.
0
7:1
MASK
Mask bits.
0x00
31:8
-
Reserved. User software should not write ones to reserved bits.
These bits read always back as zeroes.
0