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UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
91 of 808
1.
Basic configuration
GPIOs are configured using the following registers:
1. Power: always enabled.
2. Pins: See
for GPIO pins and their modes.
3. Wake-up: GPIO ports 0 and 2 can be used for wake-up if needed, see
(
).
4. Interrupts: Enable GPIO interrupts in IO0/2IntEnR (
) or IO0/2IntEnF
(
). Interrupts are enabled in the NVIC using the appropriate Interrupt Set
Enable register.
2.
Features
2.1 Digital I/O ports
•
Accelerated GPIO functions:
–
GPIO registers are located on a peripheral AHB bus for fast I/O timing.
–
Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
–
All GPIO registers are byte, half-word, and word addressable.
–
Entire port value can be written in one instruction.
–
GPIO registers are accessible by the GPDMA.
•
Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
•
All GPIO registers support Cortex-M3 bit-banding.
•
GPIO registers are accessible by the GPDMA controller to allow DMA of data to or
from GPIOs, synchronized to any DMA request.
•
Direction control of individual port bits.
•
All I/Os default to input with pullup after reset.
2.2 Interrupt generating digital ports
•
Port 0 and Port 2 can provide a single interrupt for any combination of port pins.
•
Each port pin can be programmed to generate an interrupt on a rising edge, a falling
edge, or both.
•
Edge detection is asynchronous, so it may operate when clocks are not present, such
as during Power-down mode. With this feature, level triggered interrupts are not
needed.
•
Each enabled interrupt contributes to a wake-up signal that can be used to bring the
part out of Power-down mode.
UM10360
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
Rev. 00.06 — 5 June 2009
User manual