NXP Semiconductors LPC1751, User Manual, Page: 53 / 808

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UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 53 of 808
NXP Semiconductors
UM10360
Chapter 4: LPC17xx Clocking and power control
8.7 Power Mode Control register (PCON - 0x400F C0C0)
Controls for some reduced power modes and other power related controls are contained
in the PCON register, as described in
Table 4–44 .
[1] Only one of these flags will be valid at a specific time.
[2] Hardware reset only for a power-up of core power or by a brownout detect event.
[3] Hardware reset only for a power-up event on Vbat.
Table 44. Power Mode Control register (PCON - address 0x400F C0C0) bit description
Bit Symbol Description Reset
value
0 PM0 Power mode control bit 0. This bit controls entry to the Power-down
mode. See
Section 4–8.7.1 below for details.
0
1 PM1 Power mode control bit 1. This bit controls entry to the Deep
Power-down mode. See
Section 4–8.7.1 below for details.
0
2 BODRPM Brown-Out Reduced Power Mode. When BODRPM is 1, the
Brown-Out Detect circuitry will be turned off when chip Power-down
mode or Deep Sleep mode is entered, resulting in a further reduction in
power usage. However, the possibility of using Brown-Out Detect as a
wake-up source from the reduced power mode will be lost.
When 0, the Brown-Out Detect function remains active during
Power-down and Deep Sleep modes.
See the System Control Block chapter for details of Brown-Out
detection.
0
3 BOGD Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect
circuitry is fully disabled at all times, and does not consume power.
When 0, the Brown-Out Detect circuitry is enabled.
See the System Control Block chapter for details of Brown-Out
detection.
0
4 BORD Brown-Out Reset Disable. When BORD is 1, the second stage of low
voltage detection (2.6 V) will not cause a chip reset.
When BORD is 0, the reset is enabled. The first stage of low voltage
detection (2.9 V) Brown-Out interrupt is not affected.
See the System Control Block chapter for details of Brown-Out
detection.
0
7:3 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
8 SMFLAG Sleep Mode entry flag. Set when the Sleep mode is successfully
entered. Cleared by software writing a one to this bit. 0
[1][2]
9 DSFLAG Deep Sleep entry flag. Set when the Deep Sleep mode is successfully
entered. Cleared by software writing a one to this bit. 0
[1][2]
10 PDFLAG Power-down entry flag. Set when the Power-down mode is
successfully entered. Cleared by software writing a one to this bit. 0
[1][2]
11 DPDFLAG Deep Power-down entry flag. Set when the Deep Power-down mode is
successfully entered. Cleared by software writing a one to this bit.
0
[1][3]
31:12 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA