NXP Semiconductors LPC1751, User Manual, Page: 708 / 808

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UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 708 of 808
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
‘<‘ means that accesses are observed in program order, that is, A1 is always observed
before A2.
3.2.3 Behavior of memory accesses
The behavior of accesses to each region in the memory map is:
[1] See Section 34–3.2.1 for more information.
The Code, SRAM, and external RAM regions can hold programs. However, the most
efficient access to programs is from the Code region. This is because the processor has
separate buses that enable instruction fetches and data accesses to occur
simultaneously.
The MPU can override the default memory access behavior described in this section. For
more information, see
Section 37–1.5 “Memory protection unit” .
3.2.4 Software ordering of memory accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions. This is because:
•
the processor can reorder some memory accesses to improve efficiency, providing
this does not affect the behavior of the instruction sequence.
•
the processor has multiple bus interfaces
•
memory or devices in the memory map have different wait states
•
some memory accesses are buffered or speculative.
Section 34–3.2.2 describes the cases where the memory system guarantees the order of
memory accesses. Otherwise, if the order of memory accesses is critical, software must
include memory barrier instructions to force that ordering. The processor provides the
following memory barrier instructions:
Table 607. Memory access behavior
Address
range Memory
region Memory
type XN Description
0x00000000
-
0x1FFFFFFF
Code Normal
[1]
- Executable region for program code.
You can also put data here.
0x20000000
-
0x3FFFFFFF
SRAM Normal
[1]
- Executable region for data. You can
also put code here.
This region includes bit band and bit
band alias areas, see
Table 34–608 .
0x40000000
-
0x5FFFFFFF
Peripheral Device
[1]
XN
[1]
This region includes bit band and bit
band alias areas, see
Table 34–609 .
0x60000000
-
0x9FFFFFFF
External
RAM Normal
[1]
- Executable region for data.
0xA0000000
-
0xDFFFFFFF
External
device Device
[1]
XN
[1]
External Device memory
0xE0000000
-
0xE00FFFFF
Private Peripheral
Bus Strongly-
ordered
[1]
XN
[1]
This region includes the NVIC, System
timer, and system control block.
0xE0100000
-
0xFFFFFFFF
Vendor-
specific device Device
[1]
XN
[1]
Not used for NXP devices.