NXP Semiconductors LPC1751, User Manual, Page: 41 / 808

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
FT DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
FT DRAFT DRAFT DRAFT DRA
UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 41 of 808
NXP Semiconductors
UM10360
Chapter 4: LPC17xx Clocking and power control
PLL1 activation is controlled via the PLL1CON register. PLL1 multiplier and divider values
are controlled by the PLL1CFG register. These two registers are protected in order to
prevent accidental alteration of PLL1 parameters or deactivation of PLL1. The protection
is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are
provided in the description of the PLL1FEED register.
PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input
frequency is multiplied up to the range of 48 MHz for the USB clock using a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (for USB,
the multiplier value cannot be higher than 4. The CCO operates in the range of 156 MHz
to 320 MHz, so there is an additional divider in the loop to keep the CCO within its
frequency range while PLL1 is providing the desired output frequency. The output divider
may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum
output divider value is 2, it is insured that the output of PLL1 has a 50% duty cycle. A
block diagram of PLL1 is shown in
Figure 4–9 .
6.1 PLL1 register description
PLL1 is controlled by the registers shown in Table 4–28 . More detailed descriptions follow.
Writes to any unused bits are ignored. A read of any unused bits will return a logic zero.
Warning: Improper setting of PLL1 values may result in incorrect operation of the
USB subsystem!
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Table 28. PLL1 registers
Name Description Access Reset
value
[1]
Address
PLL1CON PLL1 Control Register. Holding register for
updating PLL1 control bits. Values written to this
register do not take effect until a valid PLL1 feed
sequence has taken place. R/W 0 0x400F C0A0
PLL1CFG PLL1 Configuration Register. Holding register
for updating PLL1 configuration values. Values
written to this register do not take effect until a
valid PLL1 feed sequence has taken place. R/W 0 0x400F C0A4
PLL1STAT PLL1 Status Register. Read-back register for
PLL1 control and configuration information. If
PLL1CON or PLL1CFG have been written to,
but a PLL1 feed sequence has not yet occurred,
they will not reflect the current PL1L state.
Reading this register provides the actual values
controlling PLL1, as well as PLL1 status. RO 0 0x400F C0A8
PLL1FEED PLL1 Feed Register. This register enables
loading of PLL1 control and configuration
information from the PLL1CON and PLL1CFG
registers into the shadow registers that actually
affect PLL1 operation. WO NA 0x400F C0AC