NXP Semiconductors LPC1751, User Manual, Page: 749 / 808

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UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 749 of 808
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
4.3.11.3 Usage Fault Status Register
The UFSR indicates the cause of a usage fault. The bit assignments are shown in
Table 34–642 .
[4] STKERR Bus fault on stacking for exception entry:
0 = no stacking fault
1 = stacking for an exception entry has caused one or more bus faults.
When the processor sets this bit to 1, the SP is still adjusted but the
values in the context area on the stack might be incorrect. The
processor does not write a fault address to the BFAR.
[3] UNSTKERR Bus fault on unstacking for a return from exception:
0 = no unstacking fault
1 = unstack for an exception return has caused one or more bus faults.
This fault is chained to the handler. This means that when the processor
sets this bit to 1, the original return stack is still present. The processor
does not adjust the SP from the failing return, does not performed a new
save, and does not write a fault address to the BFAR.
[2] IMPRECISERR Imprecise data bus error:
0 = no imprecise data bus error
1 = a data bus error has occurred, but the return address in the stack
frame is not related to the instruction that caused the error.
When the processor sets this bit to 1, it does not write a fault address to
the BFAR.
This is an asynchronous fault. Therefore, if it is detected when the
priority of the current process is higher than the bus fault priority, the bus
fault becomes pending and becomes active only when the processor
returns from all higher priority processes. If a precise fault occurs before
the processor enters the handler for the imprecise bus fault, the handler
detects both IMPRECISERR set to 1 and one of the precise fault status
bits set to 1.
[1] PRECISERR Precise data bus error:
0 = no precise data bus error
1 = a data bus error has occurred, and the PC value stacked for the
exception return points to the instruction that caused the fault.
When the processor sets this bit is 1, it writes the faulting address to the
BFAR.
[0] IBUSERR Instruction bus error:
0 = no instruction bus error
1 = instruction bus error.
The processor detects the instruction bus error on prefetching an
instruction, but it sets the IBUSERR flag to 1 only if it attempts to issue
the faulting instruction.
When the processor sets this bit is 1, it does not write a fault address to
the BFAR.
Table 641. BFSR bit assignments
Bits Name Function