DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
FT DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
FT DRAFT DRAFT DRAFT DRA
UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
551 of 808
NXP Semiconductors
UM10360
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
[1]
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
5.1 A/D Control Register (AD0CR - 0x4003 4000)
ADDR7
A/D Channel 7 Data Register. This register contains the result of
the most recent conversion completed on channel 7.
RO
NA
0x4003 402C
AD0DR7
ADSTAT
A/D Status Register. This register contains DONE and
OVERRUN flags for all of the A/D channels, as well as the A/D
interrupt/DMA flag.
RO
0x0000 0000
0x4003 4030
AD0STAT
ADTRM
ADC trim register.
R/W
0x00
0x4003 4034
Table 512. ADC registers
Generic
Name
Description
Access
Reset value
[1]
AD0
Address
& Name
Table 513: A/D Control Register (AD0CR - address 0x4003 4000) bit description
Bit
Symbol Value
Description
Reset
value
7:0
SEL
Selects which of the AD0.7:0 pins is (are) to be sampled and converted. For AD0, bit 0
selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of
these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is
allowed. All zeroes is equivalent to 0x01.
0x01
15:8
CLKDIV
The APB clock (PCLK_ADC0) is divided by (this value plus one) to produce the clock for
the A/D converter, which should be less than or equal to 13 MHz. Typically, software
should program the smallest value in this field that yields a clock of 13 MHz or slightly
less, but in certain cases (such as a high-impedance analog source) a slower clock may
be desirable.
0
16
BURST
1
The AD converter does repeated conversions at up to 200 kHz, scanning (if necessary)
through the pins selected by bits set to ones in the SEL field. The first conversion after the
start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits
(pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the
conversion that’s in progress when this bit is cleared will be completed.
Remark:
START bits must be 000 when BURST = 1 or conversions will not start.
0
0
Conversions are software controlled and require 65 clocks.
20:17
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
21
PDN
1
The A/D converter is operational.
0
0
The A/D converter is in power-down mode.
23:22
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA