NXP Semiconductors LPC1751, User Manual, Page: 629 / 808

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
FT DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
FT DRAFT DRAFT DRAFT DRA
UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 629 of 808
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
2.4 Memory access instructions
Table 34–588 shows the memory access instructions:
Table 588. Memory access instructions
Mnemonic Brief description See
ADR
Load PC-relative address Section 34–2.4.1
CLREX
Clear Exclusive Section 34–2.4.9
LDM{mode}
Load Multiple registers Section 34–2.4.6
LDR{type}
Load Register using immediate offset Section 34–2.4.2
LDR{type}
Load Register using register offset Section 34–2.4.3
LDR{type}T
Load Register with unprivileged access Section 34–2.4.4
LDR
Load Register using PC-relative address Section 34–2.4.5
LDREX{type}
Load Register Exclusive Section 34–2.4.8
POP
Pop registers from stack Section 34–2.4.7
PUSH
Push registers onto stack Section 34–2.4.7
STM{mode}
Store Multiple registers Section 34–2.4.6
STR{type}
Store Register using immediate offset Section 34–2.4.2
STR{type}
Store Register using register offset Section 34–2.4.3
STR{type}T
Store Register with unprivileged access Section 34–2.4.4
STREX{type}
Store Register Exclusive Section 34–2.4.8