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CHAPTER 16 SERIAL INTERFACE UART0
User’s Manual U15798EJ2V0UD
Figure 16-1. Block Diagram of Serial Interface UART0
Note
For the configuration of the baud rate generator, refer to
Figure 16-2
.
Figure 16-2. Baud Rate Generator Block Diagram
Remark
TXE0: Bit 7 of asynchronous serial interface mode register 0 (ASIM0)
RXE0: Bit 6 of asynchronous serial interface mode register 0 (ASIM0)
Internal bus
Receive
buffer
register 0
(RXB0)
RxD0/P26
TxD0/P27
PE0 FE0 OVE0
Asynchronous serial
interface status
register 0 (ASIS0)
INTSER0
INTST0
Baud rate
generator
Note
f
X
/2 to f
X
/2
7
TXE0 RXE0 PS01 PS00 CL0
SL0 ISRM0
Asynchronous serial interface
mode register 0 (ASIM0)
INTSR0
Receive
controller
(parity
check)
Transmit
shift
register 0
(TXS0)
Transmit
controller
(parity
addition)
Receive
shift
register 0
(RX0)
TPS01
TPS02
5-bit counter
Start bit
sampling clock
TPS00
f
X
/2 to f
X
/2
7
Selector
Internal bus
3
4
MDL03
Baud rate generator
control register 0 (BRGC0)
MDL02 MDL01 MDL00
Encode
Transmit clock
TXE0
5-bit counter
Receive clock
RXE0
Start bit detection
1/2
Match
Match
1/2