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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15798EJ2V0UD
(1)
µ
PD780343, 780353, 780343Y, 780353Y
Set the value of the memory size switching register (IMS) to 46H, and the value of the internal expansion RAM
size switching register (IXS) to 0BH (default setting: IMS = CFH, IXS = 0CH).
Figure 3-1. Memory Map (
µ
PD780343, 780353, 780343Y, 780353Y)
Note
The area not used for LCD display data can be used as normal RAM.
Special function
registers (SFRs)
256
×
8 bits
Internal high-speed RAM
512
×
8 bits
LCD display RAM
40
×
8 bits
Note
Internal expansion RAM
512
×
8 bits
General-purpose
registers 32
×
8 bits
Reserved
Reserved
Reserved
Internal ROM
24,576
×
8 bits
F F F F H
F F 0 0 H
F E F F H
F E E 0 H
F E D F H
F A 2 8 H
F A 2 7 H
F D 0 0 H
F C F F H
F 6 0 0 H
F 5 F F H
F 8 0 0 H
F 7 F F H
F A 0 0 H
F 9 F F H
6 0 0 0 H
5 F F F H
0 0 0 0 H
Program
memory space
Data
memory
space
Vector table area
0 0 4 0 H
0 0 3 F H
0 0 0 0 H
CALLT table area
0 0 8 0 H
0 0 7 F H
Program area
0 8 0 0 H
0 7 F F H
CALLF entry area
1 0 0 0 H
0 F F F H
Program area
5 F F F H
