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NEC mPD780344 Series, User Manual


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User’s Manual  U15798EJ2V0UD

LIST OF FIGURES (6/8)

Figure No.

Title

Page

17-9

Start Conditions ...................................................................................................................................

320

17-10

Address ................................................................................................................................................

321

17-11

Transfer Direction Specification ...........................................................................................................

321

17-12

ACK Signal ...........................................................................................................................................

322

17-13

Stop Condition .....................................................................................................................................

323

17-14

Wait Signal ...........................................................................................................................................

324

17-15

Arbitration Timing Example ..................................................................................................................

346

17-16

Communication Reservation Timing ....................................................................................................

349

17-17

Timing for Accepting Communication Reservations ............................................................................

349

17-18

Communication Reservation Protocol ..................................................................................................

350

17-19

Master Operation Flowchart ................................................................................................................

351

17-20

Slave Operation Flowchart ...................................................................................................................

352

17-21

Example of Master to Slave Communication

(When 9-Clock Wait Is Selected for Both Master and Slave) ...............................................................

354

17-22

Example of Slave to Master Communication

(When 9-Clock Wait Is Selected for Both Master and Slave) ...............................................................

357

18-1

LCD Controller/Driver Block Diagram ..................................................................................................

362

18-2

Format of LCD Display Mode Register 3 (LCDM3) ..............................................................................

364

18-3

Blinking Function ..................................................................................................................................

365

18-4

Format of LCD Clock Control Register 3 (LCDC3) ..............................................................................

366

18-5

Relationship Between Reference Clock Generating Frame Frequency, and Frame Frequency ..........

367

18-6

Format of LCD Gain Adjust Register 0 (VLCG0) .................................................................................

367

18-7

Format of Static/Dynamic Display Switching Register 3 (SDSEL3) .....................................................

368

18-8

Format of Pin Function Switching Registers (PF8 to PF11) ................................................................

369

18-9

Relationship Between LCD Display Data, Contents of Blinking Select Bits,

 and Segment/Common Output Signals (4-Time Division) ..................................................................

370

18-10

Common Signal Waveform ..................................................................................................................

373

18-11

Common Signal and Segment Signal Voltages and Phases ...............................................................

374

18-12

Example of LCD Driver Pin Connection ...............................................................................................

375

18-13

Static LCD Panel Display Pattern and Electrode Connections ............................................................

376

18-14

Static LCD Panel Connection Example (SDSEL3n = 1: n = 0, 1) ........................................................

377

18-15

Static LCD Drive Waveform Examples .................................................................................................

378

18-16

3-Time-Division LCD Display Pattern and Electrode Connections ......................................................

379

18-17

3-Time-Division LCD Panel Connection Example (SDSEL3n = 0: n = 0 to 2) .....................................

380

18-18

3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ...................................................

381

18-19

4-Time-Division LCD Display Pattern and Electrode Connections ......................................................

382

18-20

4-Time-Division LCD Panel Connection Example (SDSEL3n = 0, n = 0 to 2) .....................................

383

18-21

4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ...................................................

384

19-1

Basic Configuration of Interrupt Function ............................................................................................

388

19-2

Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L) ...........................................................

391

19-3

Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L) .........................................................

392

19-4

Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L) .................................................

393

Summary of Contents for mPD780344 Series

Page 1: ...780354 780344Y 780354Y Subseries 8 Bit Single Chip Microcontrollers PD780343 PD780343Y PD780344 PD780344Y PD780353 PD780353Y PD780354 PD780354Y PD78F0354 PD78F0354Y Document No U15798EJ2V0UD00 2nd edi...

Page 2: ...2 User s Manual U15798EJ2V0UD MEMO...

Page 3: ...st not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs...

Page 4: ...fety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death...

Page 5: ...ch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 6841 1138 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Squa...

Page 6: ...ication of Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 0 p 140 Addition of Figure 6 11 Configuration of PPG Output and Figure 6 12 PPG Output Operation Timing pp 152 155 Modification of 6 6...

Page 7: ...Change of Caution in Figure 16 3 Format of Asynchronous Serial Interface Mode Register 0 ASIM0 p 292 Addition of baud rate calculation in Remarks in Figure 16 5 Format of Baud Rate Generator Control R...

Page 8: ...e interrupt request acknowledgment operation p 402 Addition of items in Table 19 4 Interrupt Request Enabled for Nesting During Interrupt Servicing pp 410 411 Addition of Caution and Table 20 3 HALT M...

Page 9: ...Manual Instructions Pin functions CPU functions Internal block functions Instruction set Interrupt Explanation of each instruction Other on chip peripheral functions Electrical specifications How To R...

Page 10: ...Development Software Tools User s Manuals Document Name Document No RA78K0 Assembler Package Operation U14445E Language U14446E Structured Assembly Language U11789E CC78K0 C Compiler Operation U14297...

Page 11: ...ges X13769E Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for S...

Page 12: ...8 2 2 7 P80 to P87 Port 8 48 2 2 8 P90 to P97 Port 9 48 2 2 9 P100 to P107 Port 10 49 2 2 10 P110 to P113 Port 11 49 2 2 11 AVDD 49 2 2 12 AVSS 49 2 2 13 S0 to S39 49 2 2 14 COM0 to COM3 49 2 2 15 SCO...

Page 13: ...indexed addressing 85 3 4 9 Stack addressing 86 CHAPTER 4 PORT FUNCTIONS 87 4 1 Port Functions 87 4 2 Port Configuration 89 4 2 1 Port 0 89 4 2 2 Port 1 92 4 2 3 Port 2 93 4 2 4 Port 3 96 4 2 5 Port 4...

Page 14: ...9 6 6 16 Bit Timer Event Counter 0 Cautions 151 CHAPTER 7 8 BIT TIMERS A0 B0 156 7 1 8 Bit Timer A0 B0 Functions 156 7 2 8 Bit Timer A0 B0 Configuration 157 7 3 Registers to Control 8 Bit Timer A0 B0...

Page 15: ...nverter Functions 222 12 2 8 Bit A D Converter Configuration 224 12 3 Registers to Control 8 Bit A D Converter 226 12 4 8 Bit A D Converter Operations 230 12 4 1 Basic operations of 8 bit A D converte...

Page 16: ...0344Y 780354Y SUBSERIES ONLY 306 17 1 Functions of Serial Interface IIC0 306 17 2 Serial Interface IIC0 Configuration 309 17 3 Registers to Control Serial Interface IIC0 310 17 4 I2 C Bus Mode Functio...

Page 17: ...t request acknowledge operation 399 19 4 3 Software interrupt request acknowledge operation 401 19 4 4 Nesting processing 402 19 4 5 Interrupt request hold 405 CHAPTER 20 STANDBY FUNCTION 406 20 1 Sta...

Page 18: ...CHAPTER 26 CHARACTERISTICS CURVES OF LCD CONTROLLER DRIVER REFERENCE VALUES 479 CHAPTER 27 PACKAGE DRAWINGS 481 CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS 483 APPENDIX A DEVELOPMENT TOOLS 486 A 1 Sof...

Page 19: ...7 91 4 4 Block Diagram of P10 to P17 92 4 5 Block Diagram of P20 P23 P26 93 4 6 Block Diagram of P21 P24 P27 94 4 7 Block Diagram of P22 P25 95 4 8 Block Diagram of P30 P31 97 4 9 Block Diagram of P32...

Page 20: ...Free Running Counter and One Capture Register with Both Edges Specified 142 6 16 Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter 143 6 17 Capture Operation of...

Page 21: ...ution 176 7 17 Timing of External Event Counter Operation with 16 Bit Resolution 178 7 18 Timing of Square Wave Output with 16 Bit Resolution 180 7 19 Timing of Carrier Generator Operation When CRB0 N...

Page 22: ...ling Edge Is Specified 234 12 8 A D Conversion by Software Start 235 12 9 Overall Error 236 12 10 Quantization Error 236 12 11 Example of Series Resistor String Circuit Configuration 238 12 12 Analog...

Page 23: ...SIC1 276 15 4 Timing in 3 Wire Serial I O Mode 281 15 5 Timing of Clock Data Phase 283 15 6 Output Operation of First Bit 284 15 7 Output Value of SO1 Pin Last Bit 285 16 1 Block Diagram of Serial Int...

Page 24: ...namic Display Switching Register 3 SDSEL3 368 18 8 Format of Pin Function Switching Registers PF8 to PF11 369 18 9 Relationship Between LCD Display Data Contents of Blinking Select Bits and Segment Co...

Page 25: ...ing of Reset by RESET Input 416 21 3 Timing of Reset Due to Watchdog Timer Overflow 416 21 4 Timing of Reset in STOP Mode by RESET Input 416 22 1 ROM Correction Block Diagram 419 22 2 Format of Correc...

Page 26: ...r Flash Writing Adapter with UART UART0 443 A 1 Configuration of Development Tools 487 A 2 TGC 100SDW Package Drawing for Reference Only 493 B 1 Distance Between IE System and Conversion Adapter When...

Page 27: ...f 16 Bit Timer Event Counter 0 128 6 2 TI00 P35 Pin Valid Edge and CR00 CR01 Capture Trigger 129 6 3 TI01 TO00 P34 Pin Valid Edge and CR00 Capture Trigger 129 7 1 Operation Modes 156 7 2 Configuration...

Page 28: ...17 4 Status During Arbitration and Interrupt Request Generation Timing 347 17 5 Wait Periods 348 18 1 Segment Signals and Common Signals 360 18 2 Maximum Number of Pixels Displayed 361 18 3 LCD Contr...

Page 29: ...etween PD78F0354 and 78F0354Y and Mask ROM Versions 430 23 2 Memory Size Switching Register Settings 431 23 3 Communication Mode List 434 23 4 Pin Connection List 436 24 1 Operand Identifiers and Spec...

Page 30: ...52 s 131 kHz operation subsystem clock 32 768 kHz operation 4 I O port 66 N ch open drain 6 middle voltage 4 10 bit resolution A D converter 8 channels PD780353 780354 78F0354 780353Y 780354Y 78F0354Y...

Page 31: ...D780354F1 DA3 113 pin plastic FBGA 10 10 Mask ROM PD78F0354GC 8EU 100 pin plastic LQFP fine pitch 14 14 Flash memory PD78F0354F1 DA3 113 pin plastic FBGA 10 10 Flash memory PD780343YGC 8EU 100 pin pla...

Page 32: ...62 61 60 59 58 57 56 55 54 53 52 51 P113 S39 P112 S38 P111 S37 P110 S36 P107 S35 P106 S34 P105 S33 P104 S32 P103 S31 P102 S30 P101 S29 P100 S28 P97 S27 P96 S26 P95 S25 P94 S24 P93 S23 P92 S22 P91 S21...

Page 33: ...H2 X1 K2 CAPH B3 P15 ANI5 D3 P03 INTP3 ADTRG F3 VSS1 H3 P40 K3 VLC0 B4 P20 SI3 D4 AVDD F4 IC VPP H4 VLC2 K4 VLC1 B5 P24 SO1 D5 P22 SCK3 F5 H5 S2 K5 COM1 B6 P34 TI01 TO00 D6 P26 RxD0 F6 H6 S3 K6 S0 B7...

Page 34: ...power supply VPP Programming power supply VSS0 VSS1 Ground X1 X2 Crystal main system clock XT1 XT2 Crystal subsystem clock ADTRG AD trigger input ANI0 to ANI7 Analog input AVDD Analog power supply AV...

Page 35: ...s under development Y subseries products are compatible with I2 C bus ROMless version of the PD78078 100 pin 100 pin EMI noise reduced version of the PD78078 Inverter control PD780208 100 pin VFD driv...

Page 36: ...83 8 K to 16 K 1 ch UART 1 ch 33 Inverter PD780988 16 K to 60 K 3 ch Note 1 ch 8 ch 3 ch UART 2 ch 47 4 0 V control VFD PD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2 7 V drive PD780232 16 K...

Page 37: ...Y 16 K to 60 K 2 0 V PD780078Y 48 K to 60 K 2 ch 8 ch 4 ch UART 2 ch I2 C 1 ch 52 1 8 V PD780034AY 8 K to 32 K 1 ch 3 ch UART 1 ch I2 C 1 ch 51 PD780024AY 8 ch PD78018FY 8 K to 60 K 2 ch I2 C 1 ch 53...

Page 38: ...SO3 P21 SCK3 P22 RXD0 P26 TXD0 P27 INTP0 P00 to INTP6 P06 PCL P05 ANI0 P10 to ANI7 P17 AVSS SCL0 P30 SDA0 P31 AVDD VDD0 VDD1 ADTRG P03 Note 8 Port 1 P10 to P17 8 Port 2 P20 to P27 8 Port 3 P30 to P35...

Page 39: ...Bit manipulate set reset test and Boolean operation BCD adjust etc I O port 66 CMOS input 8 CMOS I O 52Note 3 N ch open drain I O 6 Middle withstand voltage 4 A D converter 8 bit resolution 8 channels...

Page 40: ...ating ambient temperature TA 40 to 85 C Package 100 pin plastic LQFP fine pitch 14 14 113 pin plastic FBGA 10 10 The following table outlines the timer event counters for details refer to CHAPTER 6 16...

Page 41: ...uces the number of components to add to the device resulting in board space saving The mask options provided in the PD780344 780354 Subseries are shown in Table 1 1 and the mask options provided in th...

Page 42: ...is set to 1 by falling edge detection Notes 1 PD780344Y 780354Y Subseries and flash memory version cannot use an on chip pull up resistor 2 PD780344Y 780354Y Subseries only CHAPTER 2 PIN FUNCTIONS 2...

Page 43: ...iven directly On chip pull up resistor can be specified by mask option mask ROM version only P80 to P87Note I O Port 8 Input S12 to S19Note 8 bit I O port P90 to P97Note I O Port 9 Input S20 to S27Not...

Page 44: ...to capture register CR00 of 16 bit P34 TO00 timer event counter 0 TO00 Output 16 bit timer event counter 0 output P34 TI01 TMIB0 Input External count clock input to 8 bit timer event counter B0 Input...

Page 45: ...er driver common signal output Output for static display VLC0 to VLC2 LCD driving voltage VLC0 Three times VLC2 output voltage VLC1 Two times VLC2 output voltage VLC2 Reference voltage CAPH CAPL Boost...

Page 46: ...and buzzer output a INTP0 to INTP6 INTP0 to INTP6 are external interrupt request input pins for which valid edges rising edge falling edge and both rising and falling edges can be specified b ADTRG A...

Page 47: ...Port 3 These are 6 bit I O ports Besides serving as I O ports they function as serial interface data I O clock I O and timer I O 1 Port mode These ports function as 6 bit I O ports They can be specifi...

Page 48: ...mask ROM versions 2 2 7 P80 to P87 Port 8 These are 8 bit I O ports Besides serving as I O ports they function as segment signal output for dynamic display of the LCD controller driver Either the I O...

Page 49: ...1 Port mode These ports function as 4 bit I O ports They can be specified as input or output ports in 1 bit units with port mode register 11 PM11 2 Control mode These ports function as segment signal...

Page 50: ...nput pin 2 2 19 X1 and X2 Crystal resonator connection pins for main system clock oscillation For external clock supply input the clock signal to X1 and its inverted signal to X2 2 2 20 XT1 and XT2 Cr...

Page 51: ...Connect it directly to the VSS0 or VSS1 pin with the shortest possible wire in the normal operation mode When a potential difference is produced between the IC pin and VSS0 pin or VSS1 pin because the...

Page 52: ...nput Independently connect to VDD0 VDD1 VSS0 or VSS1 via P21 SO3 5 H a resistor P22 SCK3 8 C Output Leave open P23 SI1 P24 SO1 5 H P25 SCK1 8 C P26 RxD0 P27 TxD0 5 H P30 P31 PD780343 13 S Input Direct...

Page 53: ...ion of Unused Pins Type COM0 to COM3 18 B Output Leave open SCOM0 VLC0 to VLC2 CAPH CAPL RESET 2 Input XT1 16 Input Directly connect to VDD0 or VDD1 XT2 Leave open AVDD Input Directly connect to VDD0...

Page 54: ...Type 8 C Data Output disable P ch IN OUT VDD0 N ch P ch VDD0 Pullup enable Type 5 H Data Output disable P ch IN OUT VDD0 N ch Input enable P ch VDD0 Pullup enable Type 13 Q Data Output disable IN OUT...

Page 55: ...SS1 VLC0 VLC1 P ch N ch VLC2 P ch N ch P ch N ch N ch P ch OUT COM data VSS1 P ch N ch P ch N ch N ch N ch data VLC0 VLC1 SEG VLC2 P ch P ch VSS1 P ch IN OUT Data Output disable Input enable VDD0 N ch...

Page 56: ...the initial values of the memory size switching register IMS and internal expansion RAM size switching register IXS of all products PD780344 780354 780344Y and 780354Y Subseries are fixed IMS CFH IXS...

Page 57: ...gisters SFRs 256 8 bits Internal high speed RAM 512 8 bits LCD display RAM 40 8 bitsNote Internal expansion RAM 512 8 bits General purpose registers 32 8 bits Reserved Reserved Reserved Internal ROM 2...

Page 58: ...gisters SFRs 256 8 bits Internal high speed RAM 512 8 bits LCD display RAM 40 8 bitsNote Internal expansion RAM 512 8 bits General purpose registers 32 8 bits Reserved Reserved Reserved Internal ROM 3...

Page 59: ...function registers SFRs 256 8 bits Internal high speed RAM 1 024 8 bits LCD display RAM 40 8 bitsNote Internal expansion RAM 512 8 bits General purpose registers 32 8 bits Reserved Reserved Reserved F...

Page 60: ...ch upon RESET input or generation of an interrupt request are stored in the vector table area Of the 16 bit address the lower 8 bits are stored at even addresses and the higher 8 bits are stored at od...

Page 61: ...gh speed RAM can also be used as a stack memory 2 Internal expansion RAM The area F600H to F7FFH 512 bytes is assigned to the internal expansion RAM The internal expansion RAM can be used as a normal...

Page 62: ...mory and the addressing mode is illustrated in Figures 3 4 to 3 6 For details of each addressing mode see 3 4 Operand Address Addressing Figure 3 4 Correspondence Between Data Memory and Addressing PD...

Page 63: ...RAM 40 8 bitsNote Internal expansion RAM 512 8 bits General purpose registers 32 8 bits Reserved Reserved Reserved Internal ROM 32 768 8 bits F F F F H F F 0 0 H F E F F H F F 2 0 H F F 1 F H F E E 0...

Page 64: ...0 8 bitsNote Internal expansion RAM 512 8 bits General purpose registers 32 8 bits Reserved Reserved Reserved Flash memory 32 768 8 bits F F F F H F F 0 0 H F E F F H F F 2 0 H F F 1 F H F E E 0 H F E...

Page 65: ...number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H a...

Page 66: ...a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases e In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored interrupts When this flag is 0...

Page 67: ...ction when SP FEE0H b CALL CALLF and CALLT instructions when SP FEE0H c Interrupt and BRK instruction when SP FEE0H FEE0H Register pair upper Register pair lower FEDEH SP SP FEE0H FEDFH FEDEH FEE0H FE...

Page 68: ...OP rp instruction when SP FEDEH b RET instruction when SP FEDEH c RETI and RETB instructions when SP FEDDH FEE0H FEDFH FEDEH FEE0H PC15 to PC8 PC7 to PC0 FEDEH SP SP FEE0H FEDFH FEDEH FEE0H PSW PC15 t...

Page 69: ...and HL and absolute names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because of the 4 register bank configuration an...

Page 70: ...he 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved in the assembler for the 16 bit manipulation inst...

Page 71: ...W Undefined FF13H FF14H 16 bit timer counter 0 TM0 R 0000H FF15H FF16H 8 bit timer compare register 50 CR50 R W Undefined FF17H 8 bit timer compare register 51 CR51 R W Undefined FF18H 8 bit timer cou...

Page 72: ...witching register 10 PF10 R W 00H FF5BH Pin function switching register 11 PF11 R W 00H FF60H 16 bit timer mode control register 0 TMC0 R W 00H FF61H Prescaler mode register 0 PRM0 R W 00H FF62H Captu...

Page 73: ...gister 1 CSIC1 R W 10H FFE0H Interrupt request flag register 0L IF0 IF0L R W 00H FFE1H Interrupt request flag register 0H IF0H R W 00H FFE2H Interrupt request flag register 1L IF1L R W 00H FFE4H Inter...

Page 74: ...addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program c...

Page 75: ...CALL addr16 or BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to the 0800H...

Page 76: ...code are transferred to the program counter PC and branched This function is carried out when the CALLT addr5 instruction is executed This instruction references the address stored in the memory table...

Page 77: ...4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX in...

Page 78: ...ddressing Instruction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJB...

Page 79: ...with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A...

Page 80: ...mmediate data in an instruction word becoming an operand address Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE0...

Page 81: ...timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it i...

Page 82: ...H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit...

Page 83: ...ct flag RBS0 and RBS1 serve as an operand address for addressing the memory to be manipulated This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL D...

Page 84: ...RBS0 and RBS1 and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be c...

Page 85: ...t flag RBS0 and RBS1 and the sum is used to address the memory Addition is performed by expanding the B or C register contents as a positive number to 16 bits A carry from the 16th bit is ignored This...

Page 86: ...atically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved reset upon generation of an interrupt request Stack addressing enables to address the...

Page 87: ...4 1 Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as on chip hardware I O pins Figure...

Page 88: ...ter 3 PU3 Port 4 P40 to P43 I O port Input output mode can be specified in 1 bit units An on chip pull up resistor can be used in 1 bit units by setting pull up resistor option register 4 PU4 Sets the...

Page 89: ...oftware control 24 4 2 1 Port 0 Port 0 is an 8 bit I O port with an output latch The P00 to P07 pins can be set to input mode output mode in 1 bit units using port mode register 0 PM0 An on chip pull...

Page 90: ...to P04 PU Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal Internal bus VDD0 P ch P00 INTP0 P01 INTP1 P02 INTP2 P03 INTP3 ADTRG P04 INTP4 WRPU RD WR...

Page 91: ...P07 PU Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal Internal bus VDD0 P ch P05 INTP5 PCL P06 INTP6 TOB0 P07 TOA0 TMIB0 WRPU RD WRPORT WRPM PU05 t...

Page 92: ...2 2 Port 1 Port 1 is an 8 bit input only port This port can also be used for A D converter analog input Figure 4 4 shows a block diagram of port 1 Figure 4 4 Block Diagram of P10 to P17 RD Port 1 read...

Page 93: ...be used for serial interface data I O and clock I O RESET input sets port 2 to input mode Figures 4 5 to 4 7 show block diagrams of port 2 Caution When P23 SI1 P24 SO1 and P25 SCK1 are used as general...

Page 94: ...agram of P21 P24 P27 PU Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal RD Internal bus P21 SO3 P24 SO1 P27 TxD0 P ch WRPU WRPORT WRPM PU21 PU24 PU2...

Page 95: ...Diagram of P22 P25 PU Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal Internal bus P22 SCK3 P25 SCK1 WRPUB2 RD WRPORT WRPM PU22 PU25 Alternate func...

Page 96: ...p resistor option register 3 PU3 These pins can also be used for timer I O RESET input sets port 3 to input mode Table 4 3 lists the port 3 pin function of each product and Figures 4 8 to 4 10 show bl...

Page 97: ...P31 PM30 PM31 Selector VDD0 Mask option resistor Mask ROM version only No pull up resistor for flash memory version b PD780344Y 780354Y Subseries Internal bus P30 SCL0 P31 SDA0 RD WRPORT WRPM Alternat...

Page 98: ...P34 PU Pull up resistor option register PM Port mode register RD Port 3 read signal WR Port 3 write signal Internal bus VDD0 P ch P32 TI51 TO51 P33 TI50 TO50 P34 TI01 TO00 WRPU RD WRPORT WRPM PU32 to...

Page 99: ...J2V0UD Figure 4 10 Block Diagram of P35 PU Pull up resistor option register PM Port mode register RD Port 3 read signal WR Port 3 write signal Internal bus VDD0 P ch P35 TI00 WRPU RD WRPORT WRPM PU35...

Page 100: ...ns 1 When using the falling edge detection interrupt INTKR be sure to set the memory expansion mode register MEM to 01H 2 The falling edge can be detected only when a falling edge occurs while all the...

Page 101: ...ull up resistor can be set by mask option The P70 to P73 pins can drive LEDs directly RESET input sets port 7 to input mode Figure 4 13 shows a block diagram of port 7 Figure 4 13 Block Diagram of P70...

Page 102: ...t This port can be switched between an I O port and a segment output port in 1 bit units by pin function switching register 8 PF8 RESET input sets port 8 to input mode Figure 4 14 shows a block diagra...

Page 103: ...t This port can be switched between an I O port and a segment output port in 1 bit units by pin function switching register 9 PF9 RESET input sets port 9 to input mode Figure 4 15 shows a block diagra...

Page 104: ...is port can switched between an I O port and a segment output port in 1 bit units by pin function switching register 10 PF10 RESET input sets port 10 to input mode Figure 4 16 shows a block diagram of...

Page 105: ...port can be switched between an I O port and a segment output port in 1 bit units by pin function switching register 11 PF11 RESET input sets port 11 to input mode Figure 4 17 shows a block diagram of...

Page 106: ...in 1 bit units PM0 PM2 to PM4 and PM7 to PM11 are independently set by a 1 bit or 8 bit memory manipulation instruction RESET input sets the values of these registers to FFH Cautions 1 The P10 to P17...

Page 107: ...R W Symbol 7 6 5 4 3 2 1 0 PM7 1 1 1 1 PM73 PM72 PM71 PM70 Address FF28H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM8Note PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80 Address FF29H After reset FFH R W Sy...

Page 108: ...sed with a pull up resistor by setting a mask option only for mask ROM versions of the PD780344 780354 Subseries 4 When PUm is set to 1 an on chip pull up resistor is connected irrespective of the inp...

Page 109: ...ulation instruction RESET input sets the value of this register to 00H Figure 4 20 Format of Memory Expansion Mode Register MEM MM2 MM1 MM0 Single chip key return mode selection 0 0 0 Single chip mode...

Page 110: ...s segment output pins by PF8 to PF11 can output their signals regardless of the value of the corresponding port mode register PM8 to PM11 2 PF8 to PF11 can be set only once after a reset To change the...

Page 111: ...The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not chan...

Page 112: ...4 Comparison Between Mask ROM Version and Flash Memory Version Pin Name Mask ROM Version of Mask ROM Version of Flash Memory Version PD780344 780354 Subseries PD780344Y 780354Y Subseries P30 P31 pins...

Page 113: ...tor The circuit oscillates at a frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used the internal feedback resistor can be disabled by the processor cloc...

Page 114: ...fX 2 fX 22 fX 23 fX 24 fXTT 2 1 2 SCT 4 multiplication circuit Prescaler Timer 51 watch timer clock output function LCD controller driver Subclock select register SSCK Clock to peripheral hardware CP...

Page 115: ...main system clock oscillator operation stop and whether to use the subsystem clock oscillator internal feedback resistorNote PCC is set by a 1 bit or 8 bit memory manipulation instruction RESET input...

Page 116: ...T 2 0 0 1 2fXT when 4 circuit is used 0 1 0 0 1 1 1 0 0 Other than above Setting prohibited Notes 1 Bit 5 is a read only bit 2 When the CPU is operating on the subsystem clock MCC should be used to st...

Page 117: ...on instruction RESET input sets this register to 00H Figure 5 4 Format of Subclock Select Register Symbol 7 6 5 4 3 2 1 0 Address After reset R W SSCK 0 0 0 0 0 0 0 SCT FF78H RetainedNote R W SCT Cont...

Page 118: ...xecute the STOP instruction and do not set MCC bit 7 of processor clock control register PCC to 1 if an external clock is input This is because when the STOP instruction or MCC is set to 1 the main sy...

Page 119: ...z XT1 XT2 External clock VSS1 Caution When using the main system clock oscillator and subsystem clock oscillator wire as follows in the area enclosed by the broken lines in the Figures 5 5 and 5 6 to...

Page 120: ...a Too long wiring b Crossed signal line c Wiring near high fluctuating current d Current flowing through ground line of oscillator potential at points A B and C fluctuates Remark When using the subsy...

Page 121: ...4 Divider The divider divides the main system clock oscillator output fX and generates various clocks 5 4 5 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low po...

Page 122: ...P mode the subsystem clock feedback resistor can be disconnected to stop the subsystem clock d The PCC can be used to select the subsystem clock and to operate the system with low power consumption 12...

Page 123: ...S of PCC is set to 1 the subsystem clock operation is started CLS 1 and then bit 7 MCC of PCC is set to 1 c If bit 7 MCC of the PCC is set to 1 when operated with the main system clock the main system...

Page 124: ...lowing operations are carried out a The minimum instruction execution time is either of the following depending on the setting of the subclock select register SSCK 122 s at 32 768 kHz operation 30 5 s...

Page 125: ...ot be set simultaneously Simultaneous setting is possible however for selection of the CPU clock cycle division ratio PCC0 to PCC2 and switchover from the subsystem clock to the main system clock chan...

Page 126: ...s rewritten and maximum speed operation is carried out 3 Upon detection of a decrease of the VDD voltage due to an interrupt request signal the main system clock is switched to the subsystem clock whi...

Page 127: ...0 16 bit timer event counter 0 has the following functions Interval timer PPG output Pulse width measurement External event counter Square wave output 1 Interval timer Generates an interrupt request...

Page 128: ...3 PM3 Note Note Refer to Figure 4 9 Block Diagram of P32 to P34 and Figure 4 10 P35 Block Diagram Figure 6 1 shows a block diagram Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 0 Internal bu...

Page 129: ...nerated if they match It can also be used as the register which holds the interval time when TM0 is set to interval timer operation When CR00 is used as a capture register It is possible to select the...

Page 130: ...capture register and a compare register Whether it is used as a capture register or a compare register is set by bit 2 CRC02 of capture compare control register 0 CRC0 When CR01 is used as a compare...

Page 131: ...r mode register 0 PRM0 Port mode register 3 PM3 1 16 bit timer mode control register 0 TMC0 This register sets the 16 bit timer operation mode the 16 bit timer counter 0 TM0 clear mode and output timi...

Page 132: ...en TM0 and CR01 OVF0 16 bit timer counter 0 TM0 overflow detection 0 Overflow not detected 1 Overflow detected Cautions 1 Be sure to stop timer operation before writing to bits other than the OVF0 fla...

Page 133: ...tes as capture register CRC01 CR00 capture trigger selection 0 Captures on valid edge of TI01 1 Captures on valid edge of TI00 by reverse phase CRC00 CR00 operation mode selection 0 Operates as compar...

Page 134: ...TOC0 Address FF63H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TOC0 0 0 0 TOC04 LVS0 LVR0 TOC01 TOE0 TOC04 Timer output F F control by match of CR01 and TM0 0 Inversion operation disabled 1 Inversion...

Page 135: ...X 22 2 5 MHz 1 0 fX 26 156 25 kHz 1 1 TI00 valid edgeNote Note The external clock requires a pulse longer than two internal clock cycles fX 23 Cautions 1 If the valid edge of TI00 is to be set as the...

Page 136: ...set PM30 and the output latch of P30 to 0 PM3 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets the value of this register to FFH Figure 6 6 Format of Port Mode Register 3 P...

Page 137: ...alue cleared to 0 and the interrupt request signal INTTM00 is generated The count clock of 16 bit timer event counter 0 can be selected with bits 0 and 1 PRM00 PRM01 of prescaler mode register 0 PRM0...

Page 138: ...Clear circuit INTTM00 fX fX 22 fX 26 TI00 P35 Selector Noise eliminator fX 2 3 Figure 6 9 Timing of Interval Timer Operation Count clock t TM0 count value CR00 INTTM00 TO00 0000H 0001H N 0000H 0001H...

Page 139: ...gs for PPG Output Operation a 16 bit timer mode control register 0 TMC0 0 0 0 0 TMC03 1 TMC02 1 0 OVF0 0 TMC0 Clears and starts on match between TM0 and CR00 b Capture compare control register 0 CRC0...

Page 140: ...t timer capture compare register 00 CR00 16 bit timer counter 0 TM0 Clear circuit Noise eliminator fX 23 fX fX 22 fX 26 TI00 P35 16 bit timer capture compare register 01 CR01 TO00 TI01 P34 Selector Ou...

Page 141: ...nto 16 bit timer capture compare register 01 CR01 and an external interrupt request signal INTTM01 is set Any of three edges can be selected rising falling or both edges specified by means of bits 4 a...

Page 142: ...counter 0 TM0 OVF0 16 bit timer capture compare register 01 CR01 Internal bus INTTM01 Selector Figure 6 15 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture Register...

Page 143: ...mpare register 00 CR00 and an external interrupt request signal INTTM00 is set Any of three edges can be selected rising falling or both edges as the valid edges for the TI00 P35 pin and the TI01 TO00...

Page 144: ...fied Figure 6 18 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges Specified Count clock TM0 TI00 Rising edge detection CR01 INTTM01 n 3 n 2 n 1 n n 1 n t 0000H 000...

Page 145: ...g or falling as the valid edge for the TI00 P35 pin specified by means of bits 4 and 5 ES00 and ES01 of prescaler mode register 0 PRM0 Sampling is performed at the interval selected by means of presca...

Page 146: ...igure 6 21 The edge specification can be selected from two types rising and falling edges by bits 4 and 5 ES00 and ES01 of prescaler mode register 0 PRM0 In a valid edge detection the sampling is perf...

Page 147: ...f TI00 P35 pin b Capture compare control register 0 CRC0 0 0 0 0 0 CRC02 1 CRC01 1 CRC00 1 CRC0 CR00 used as capture register Captures to CR00 at edge reverse to valid edge of TI00 P35 CR01 used as ca...

Page 148: ...t be carried out The rising edge the falling edge or both edges can be selected with bits 4 and 5 ES00 and ES01 of prescaler mode register 0 PRM0 Because capture operation is carried out only after th...

Page 149: ...g Edge Specified TI00 pin input TM0 count value CR00 INTTM00 0000H 0001H 0002H 0003H 0004H 0005H N 1 N 0000H 0001H 0002H 0003H N Caution When reading the external event counter count value TM0 should...

Page 150: ...compare register c 16 bit timer output control register 0 TOC0 0 0 0 TOC04 0 LVS0 0 1 LVR0 0 1 TOC01 1 TOE0 1 TOC0 Enables TO00 output Reverses output on match between TM0 and CR00 Specifies initial...

Page 151: ...et 16 bit timer capture compare registers 00 01 CR00 CR01 to other than 0000H This means a 1 pulse count operation cannot be performed when the timer is used as an event counter 3 Operation after comp...

Page 152: ...upon detection of the valid edge Figure 6 30 Capture Register Data Retention Timing Count clock TM0 count Edge input INTTM01 Capture read signal CR01 captured value N N 1 N 2 M M 1 M 2 X N 1 Capture...

Page 153: ...0000H Figure 6 31 Operation Timing of OVF0 Flag Count clock CR00 TM0 OVF0 INTTM00 FFFFH FFFEH FFFFH 0000H 0001H 2 Even if the OVF0 flag is cleared before the next count clock before TM0 becomes 0001H...

Page 154: ...not performed 3 To ensure the reliability of the capture operation the capture trigger requires a pulse longer than two of the count clock cycles selected by prescaler mode register 0 PRM0 4 The captu...

Page 155: ...ture trigger In the former case the sampling clock is fX 23 and because the main system clock is used the sampling clock can only be used when the main system clock is operating In the latter case sam...

Page 156: ...1 8 bit timer counter mode discrete mode The following functions can be used in this mode Interval timer with 8 bit resolution External event counter with 8 bit resolution timer B0 only Square wave o...

Page 157: ...onfiguration of 8 Bit Timer A0 B0 Item Configuration Timer counters 8 bits 2 TMA0 TMB0 Registers Compare registers 8 bits 3 CRA0 CRB0 CRHB0 Timer input 1 TMIB0 Timer output 2 TOA0 TOB0 Control registe...

Page 158: ...ch signal during cascade connection mode From Figure 7 2 D Count operation start signal during cascade connection mode INTTMA0 fX 24 fX 26 Timer B0 interrupt request signal from Figure 7 2 B Carrier c...

Page 159: ...RMCB0 NRZBB0 NRZB0 Carrier generator output control register B0 TCAB0 To Figure 7 1 D count clock input signal to TMA0 Internal reset signal INTTMB0 To Figure 7 1 A Bit 7 of TMB0 during cascade connec...

Page 160: ...CRA0 cannot be used in PWM output mode 2 8 bit compare register B0 CRB0 This 8 bit register is used to continually compare the value set to CRB0 with the count value in 8 bit timer counter B0 TMB0 and...

Page 161: ...When the TMA0 count value overflows ii TMB0 After reset When TCEB0 bit 7 of 8 bit timer mode control register B0 TMCB0 is cleared to 0 When a match occurs between TMB0 and CRB0 When the TMB0 count va...

Page 162: ...gisters to Control 8 Bit Timer A0 B0 8 bit timer A0 and B0 are controlled by the following four registers 8 bit timer mode control register A0 TMCA0 8 bit timer mode control register B0 TMCB0 Carrier...

Page 163: ...arrier clock in carrier generator mode or timer B0 output signal in other than carrier generator mode TMDA00 TMDB01 TMDB00 Selection of operation mode for timer A0 and timer B0Note 2 0 0 0 8 bit timer...

Page 164: ...nection mode TCLB02 TCLB01 TCLB00 Selection of timer B0 count clock 0 0 0 fX 22 2 5 MHz 0 0 1 fX 23 1 25 MHz 0 1 0 fTMI 0 1 1 fTMI 2 1 0 0 fTMI 22 1 0 1 fTMI 23 Other than above Setting prohibited TMD...

Page 165: ...to TOB0 INTP6 P06 pin carrier clock is stopped 1 A carrier clock or high level signal is output to TOB0 INTP6 P06 pin Cautions 1 TCAB0 cannot be set by a 1 bit memory manipulation instruction Be sure...

Page 166: ...operate 8 bit timer n0 as an interval timer settings must be made in the following sequence 1 Disable operation of 8 bit timer counter n0 TMn0 TCEn0 0 2 Disable timer output of TOn0 TOEn0 0 3 Set the...

Page 167: ...0 0 0 22 fX 0 4 s 210 fX 102 ms 22 fX 0 4 s 0 0 1 23 fX 0 8 s 211 fX 205 ms 23 fX 0 8 s 0 1 0 fTMI input cycle fTMI input cycle 28 fTMI input cycle 0 1 1 fTMI 2 input cycle fTMI 2 input cycle 28 fTMI...

Page 168: ...When CRn0 Is Set to 00H Count clock CRn0 TCEn0 INTTMn0 TOn0 00H TMn0 00H Count start Remark n A B Figure 7 10 Timing of Interval Timer Operation with 8 Bit Resolution When CRn0 Is Set to FFH Count cl...

Page 169: ...00H 01H M N M N M Clear Clear Clear Count start Interrupt acknowledgement Interrupt acknowledgement CRn0 overwritten Remarks 1 n A B 2 00H N M FFH Figure 7 12 Timing of Interval Timer Operation with...

Page 170: ...en Timer B0 Match Signal Is Selected for Timer A0 Count Clock Timer B0 count clock CRB0 TCEB0 INTTMB0 TOB0 TMB0 N 00H M 00H 00H 01H M N M 00H M 00H 00H 01H Y 1 Y 00H Y 00H Y Input clock to timer A0 ti...

Page 171: ...ures 7 4 and 7 5 6 Set a count value in CRB0 7 Enable the operation of TMB0 TCEB0 1 Caution This operation only applies to timer B0 Timer A0 cannot be used as an external event counter because it does...

Page 172: ...e TOn0 pin output status will be inverted Through application of this mechanism square waves of any frequency can be output As soon as a match occurs TMn0 is cleared to 00H and continues counting At t...

Page 173: ...TCEn0 INTTMn0 TOn0Note N TMn0 N 00H 01H N 00H 01H N 00H 01H 00H 01H Clear Clear Clear Count start Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement Square wave output cycle...

Page 174: ...ence 1 Disable operation of 8 bit timer counter A0 TMA0 and 8 bit timer counter B0 TMB0 TCEA0 0 TCEB0 0 2 Disable timer output of TOA0 TOB0 TOEA0 0 TOEB0 0 3 Set the count clock for timer B0 see Table...

Page 175: ...219 fX 52 4 ms 23 fX 0 8 s 0 1 0 fTMI input cycle fTMI input cycle 216 fTMI input cycle 0 1 1 fTMI 2 input cycle fTMI 2 input cycle 216 fTMI 2 input cycle 1 0 0 fTMI 22 input cycle fTMI 22 input cycle...

Page 176: ...clock TMB0 count value CRB0 TCEB0 INTTMB0 TOB0 FFH 00H 7FH 00H N 00H N N N N 80H 7FH 80H FFH 00H N 00H N N N TMA0 count clock TMA0 count value 00H X X 1 01H CRA0 X X X 7FH 80H FFH 00H N 00H N N N X X...

Page 177: ...e operation mode of timer A0 and timer B0 to 16 bit timer counter mode see Figures 7 4 and 7 5 6 Set a count value in CRA0 and CRB0 7 Enable the operation of TMA0 and TMB0 TCEB0 1Note Note Start and c...

Page 178: ...ount value CRB0 TCEB0 INTTMB0 FFH 00H 7FH 00H N 00H N N N N 80H 7FH 80H FFH 00H N 00H N N N TMA0 count clock TMA0 count value 00H X 01H CRA0 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H X 1 Not cleared...

Page 179: ...be inverted Through application of this mechanism square waves of any frequency can be output As soon as a match occurs TMA0 and TMB0 are cleared to 00H and counting continues At the same time an int...

Page 180: ...FH TMB0 count clock TMB0 count value CRB0 TCEB0 INTTMB0 TOB0Note FFH 00H 7FH 00H N 00H N N N N 80H 7FH 80H FFH 00H N 00H N N N TMA0 count clock TMA0 count value 00H X X 1 01H CRA0 X X X 7FH 80H FFH 00...

Page 181: ...the carrier generator is as follows 1 When the count value of TMB0 matches the value set in CRB0 an interrupt request signal INTTMB0 is generated and output status of timer B0 is inverted which makes...

Page 182: ...emarks 1 00H N M FFH 2 L 00H to FFH TMB0 count clock TMB0 count value CRB0 TCEB0 INTTMB0 M 00H N 00H 01H N CRHB0 M N 00H Carrier clock N 00H 00H N M 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TMA0 co...

Page 183: ...Remarks 1 00H M N FFH 2 L 00H to FFH TMB0 count clock TMB0 count value CRB0 TCEB0 INTTMB0 N 00H N CRHB0 M Carrier clock N 00H 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TMA0 count value CRA0 TCEA0 I...

Page 184: ...N Remark N L 00H to FFH TMB0 count clock TMB0 count value CRB0 TCEB0 INTTMB0 N 00H 00H 00H N CRHB0 N N Carrier clock 00H 00H N N 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TMA0 count value CRA0 TCEA0...

Page 185: ...TOB0 TOEB0 1 7 Enable the operation of TMB0 TCEB0 1 The operation in the PWM output mode is as follows 1 When the count value of TMB0 matches the value set in CRB0 an interrupt request signal INTTMB0...

Page 186: ...ng When CRB0 and CRHB0 Are Overwritten Note The initial value of TOB0 is low level when output is enabled TOEB0 1 Remark N M X Y 00H to FFH TMB0 count clock TMB0 count value CRB0 TCEB0 INTTMB0 00H N 0...

Page 187: ...solution Count pulse CRn0 00H TMn0 count value 00H 00H 00H 00H INTTMn0 Remark n A B 3 Count value if timer is started when TMIB0 pin is high When an external clock input from the TMIB0 pin is selected...

Page 188: ...50 and 51 8 bit timer event counters 50 and 51 have the following functions Interval timer External event counter Square wave output PWM output 1 Interval timer These counters generate interrupt requ...

Page 189: ...ernal bus TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 Invert level 8 bit timer mode control register 50 TMC50 S R S Q R INV Selector INTTM50 TO50 TI50 P33 Selector 8 bit timer counter 50 TM50 Selector Inter...

Page 190: ...clock When the count value is read during operation count clock input is temporary stopped and then the count value is read In the following situations the count value is set to 00H 1 RESET input 2 Wh...

Page 191: ...t TCL5n is set by an 8 bit memory manipulation instruction RESET input sets the value of this register to 00H Figure 8 3 Format of Timer Clock Select Register 50 TCL50 Address FF71H After reset 00H R...

Page 192: ...op the timer operation beforehand 2 Be sure to set bits 3 to 7 to 0 Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses are for operation with fX 10 MHz fXT 32 768 kHz 2 8 bi...

Page 193: ...de selection 0 Clear and start mode by matching between TM5n and CR5n 1 PWM free running mode LVS5n LVR5n Timer output F F status setting 0 0 No change 0 1 Timer output F F reset 0 1 0 Timer output F...

Page 194: ...tput set PM33 PM32 and the output latches of P33 and P32 to 0 PM3 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets the value of this register to FFH Figure 8 6 Format of Por...

Page 195: ...Timer Event Counter 50 and 51 Cautions 2 about the operation when the compare register value is changed during timer count operation Setting 1 Set the registers TCL5n Select count clock CR5n Compare v...

Page 196: ...mer Operation Timings 2 3 b When CR5n 00H t Count clock TM5n CR5n TCE5n INTTM5n TO5n Interval time 00H 00H 00H 00H 00H c When CR5n FFH t Count clock TM5n CR5n TCE5n INTTM5n TO5n 01 FE FF 00 FE FF 00 F...

Page 197: ...ration Timings 3 3 d Operated by CR5n transition M N Count clock TM5n CR5n TCE5n INTTM5n TO5n 00H N N M N FFH 00H M 00H M CR5n transition TM5n overflows since M N H e Operated by CR5n transition M N C...

Page 198: ...e matches the value of CR5n INTTM5n is generated Setting 1 Set each register TCL5n Select TI5n input edge TI5n falling edge TCL5n 00H TI5n rising edge TCL5n 01H CR5n Compare value TMC5n Stop the count...

Page 199: ...and start mode by match of TM5n and CR5n LVS5n LVR5n Timer Output F F Status Setting 1 0 High level output 0 1 Low level output Timer output F F reverse enable Timer output enable TOE5n 1 TMC5n 00001...

Page 200: ...s PM32 PM33 Note to 0 TCL5n Select the count clock CR5n Compare value TMC5n Stop the count operation select PWM mode The timer output F F is not changed TMC5n1 Active Level Selection 0 Active high 1 A...

Page 201: ...01H 02H N N 1 FFH 00H 01H 02H M 00H N Active level Active level Inactive level b CR5n 0 c CR5n FFH Remark n 0 1 Count clock TM5n CR5n TCE5n INTTM5n TO5n L Inactive level Inactive level 01H 00H FFH 00H...

Page 202: ...2 FFH 00H 01H M M 1 M 2 FFH 00H 01H 02H M M 1 M 2 N 02H M H b CR5n value shifts from N to M after overflow of TM5n c CR5n value shifts from N to M between two clocks 00H and 01H after overflow of TM5...

Page 203: ...bit timer counter 5n TM5n TM5n continues counting overflows and then restarts counting from 0 Thus if the value M after CR5n change is smaller than value N before the change it is necessary to restart...

Page 204: ...the watch timer block diagram Figure 9 1 Watch Timer Block Diagram Remark fX Main system clock oscillation frequency fXT Subsystem clock oscillation frequency fW Watch timer clock frequency fX 28 fXT...

Page 205: ...W 819 2 s 977 s 1 95 ms 213 fW 0 2 s 0 25 s 0 5 s 214 fW 0 41 s 0 5 s 1 0 s Remark fW Watch timer clock frequency fX 28 fXT or fXT 2 fX Main system clock oscillation frequency fXT Subsystem clock osci...

Page 206: ...ect register WTIM 9 4 Registers to Control Watch Timer The following two registers are used to control the watch timer Watch timer operation mode register 0 WTNM0 Watch timer interrupt time select reg...

Page 207: ...19 fX 52 4 ms 211 fXT 62 4 ms 212 fXT 125 ms WTNM03 WTNM02 Selection of interrupt request time of the watch timer WTNM07 0 WTNM07 1 WTS 0 WTS 1 0 0 214 fW 222 fX 0 41 s 214 fXT 0 5 s 215 fXT 1 0 s 0 1...

Page 208: ...set by a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 9 3 Format of Watch Timer Interrupt Time Select Register WTIM Symbol 7 6 5 4 3 2 1 0 Address After...

Page 209: ...nce the 11 bit prescaler is not cleared at the first overflow INTWTN0 after the watch timer s zero second start an error of up to 211 1 fW seconds occurs 9 5 2 Interval timer operation The watch timer...

Page 210: ...lect the watchdog timer mode or the interval timer mode with the watchdog timer mode register WDTM The watchdog timer and the interval timer cannot be used simultaneously Figure 10 1 shows a block dia...

Page 211: ...216 1 fX 6 55 ms 217 1 fX 13 1 ms 218 1 fX 26 2 ms 220 1 fX 105 ms Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses are for operation with fX 10 MHz 2 Interval timer mode...

Page 212: ...figuration Control registers Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Oscillation stabilization time select register OSTS 10 4 Registers to Control Watchdog Timer Th...

Page 213: ...ure 10 2 Format of Watchdog Timer Clock Select Register WDCS Address FF42H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 WDCS2 WDCS1 WDCS0 Overflow time of watchdog timer...

Page 214: ...n mode selectionNote 2 0 Interval timer modeNote 3 Maskable interrupt request occurs upon generation of an overflow 1 0 Watchdog timer mode 1 Non maskable interrupt request occurs upon generation of a...

Page 215: ...when releasing the STOP mode by RESET input the time required to release is 217 fX Figure 10 4 Format of Oscillation Stabilization Time Select Register OSTS Address FFFAH After reset 04H R W Symbol 7...

Page 216: ...etection time is exceeded system reset or a non maskable interrupt request is generated according to WDTM bit 3 WDTM3 value The watchdog timer continues operating in the HALT mode but it stops in the...

Page 217: ...maskable interrupts INTWDT has the highest priority at default The interval timer continues operating in the HALT mode but it stops in STOP mode Thus set RUN to 1 before the STOP mode is set clear the...

Page 218: ...tput controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs The clock selected with the clock output select register CKS is outp...

Page 219: ...Port mode register 0 PM0 Note Note See Figure 4 3 P05 to P07 Block Diagram 11 4 Registers to Control Clock Output Controller The following two registers are used to control the clock output controlle...

Page 220: ...l 1 Enable clock division circuit operation PCL output enabled CCS3 CCS2 CCS1 CCS0 PCL output clock selection 0 0 0 0 fX 10 MHz 0 0 0 1 fX 2 5 MHz 0 0 1 0 fX 22 2 5 MHz 0 0 1 1 fX 23 1 25 MHz 0 1 0 0...

Page 221: ...ut mode output buffer ON 1 Input mode output buffer OFF 11 5 Clock Output Controller Operations The clock pulse is output using the following procedure 1 Select the clock pulse output frequency with b...

Page 222: ...art Conversion is started by setting A D converter mode register 0 ADM0 Select one channel for analog input from ANI0 to ANI7 to perform A D conversion In the case of hardware start A D conversion sto...

Page 223: ...Falling Edge Enable Register EGN ANI0 P10 ANI1 P11 ANI2 P12 ANI3 P13 ANI4 P14 ANI5 P15 ANI6 P16 ANI7 P17 Sample hold circuit Voltage comparator Successive approximation register SAR Controller Edge d...

Page 224: ...stores the A D conversion result Each time A D conversion ends the conversion result is loaded from the successive approximation register ADCR1 is read by an 8 bit memory manipulation instruction RES...

Page 225: ...conversion as this may cause a lower conversion resolution 3 When a digital pulse is applied to a pin adjacent to the pin being A D converted A D conversion values may not be obtained as expected due...

Page 226: ...control the 8 bit A D converter A D converter mode register 0 ADM0 Analog input channel specification register 0 ADS0 1 A D converter mode register 0 ADM0 This register sets the conversion time for t...

Page 227: ...dge specification 0 0 No edge detection 0 1 Falling edge detection 1 0 Rising edge detection 1 1 Both falling and rising edge detection ADCE0 Control of voltage booster for A D converter circuitNote 3...

Page 228: ...on mode reference voltage generator operates Note Data of the first conversion cannot be used immediately after A D conversion is started Figure 12 3 Timing Chart When Boost Reference Voltage Generato...

Page 229: ...D conversion ADS0 is set by an 8 bit memory manipulation instruction RESET input sets ADS0 to 00H Figure 12 4 Format of Analog Input Channel Specification Register 0 ADS0 Address FF81H After reset 00...

Page 230: ...AR remains set If the analog input is smaller than 1 2 AVDD the MSB is reset 6 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison The series resistor string volta...

Page 231: ...e performed continuously until bit 7 ADCS0 of A D converter mode register 0 ADM0 is reset 0 by software If a write operation is performed to ADM0 or analog input channel specification register 0 ADS0...

Page 232: ...VIN 256 0 5 AVDD or ADCR1 0 5 AVDD VAIN ADCR1 0 5 AVDD 256 256 where INT Function which returns integer part of value in parentheses VAIN Analog input voltage AVDD AVDD pin voltage ADCR1 A D conversi...

Page 233: ...TRG is input A D conversion of the voltage applied to the analog input pins specified by analog input channel specification register 0 ADS0 starts Upon the end of the A D conversion the conversion res...

Page 234: ...V0UD Figure 12 7 A D Conversion by Hardware Start When Falling Edge Is Specified Remarks 1 n 0 1 7 2 m 0 1 7 A D conversion ADCR1 ADTRG INTAD0 ADM0 set ADCE0 1 ADCS0 1 TRG0 1 Standby state ANIn ANIn A...

Page 235: ...st signal INTAD0 is generated After one A D conversion operation is started and ended the next conversion operation is immediately started A D conversion operations are repeated until new data is writ...

Page 236: ...and the theoretical value Zero scale error full scale error integral linearity error differential linearity error and errors which are combi nations of these express overall error Furthermore quantiza...

Page 237: ...the time from when sampling is started to the time when the digital output was obtained Sampling time is included in the conversion time in the characteristics table 5 Sampling time This is the time t...

Page 238: ...the absolute maximum rating range the conversion value of that channel will be undefined and the conversion values of other channels may also be affected 3 Conflicting operations 1 Conflict between A...

Page 239: ...ay reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin being A D converted the expected A D conversion value may not be obtainable due to coupling noise Th...

Page 240: ...Im ANIn ANIn ANIm ANIm ADS0 rewrite start of ANIm conversion ADIF is set but ANIm conversion has not ended Remarks 1 n 0 1 7 2 m 0 1 7 9 Conversion results just after A D conversion start If bit 7 ADC...

Page 241: ...ng of Reading Conversion Result When Conversion Result Is Normal 12 Notes on board design Locate analog circuits as far away from digital circuits as possible on the board because the analog circuits...

Page 242: ...nd AVSS pins Figure 12 16 shows an example of connecting a capacitor Figure 12 16 Example of Connecting Capacitor to AVDD Pin Remark C1 4 7 F to 10 F reference value C2 0 01 F to 0 1 F reference value...

Page 243: ...crocontroller cannot follow an analog signal with a high differential coefficient because a lowpass filter is created To convert a high speed analog signal or to convert an analog signal in the scan m...

Page 244: ...enerated In the case of software start A D conversion is repeated Each time as A D conversion operation ends an interrupt request INTAD0 is generated Figure 13 1 10 Bit A D Converter Block Diagram Not...

Page 245: ...ve approximation register The result is stored in ADCR0 in order from the most significant bit MSB The higher 8 bits of the conversion result are input to FF0FH and the lower 2 bits of the conversion...

Page 246: ...e to coupling noise Thus do not apply any pulse to a pin adjacent to the pin being A D converted 7 AVDD pin This pin inputs the A D converter analog power supply Use this pin at the same potential as...

Page 247: ...edge specification 0 0 No edge detection 0 1 Falling edge detection 1 0 Rising edge detection 1 1 Both falling and rising edge detection ADCE0 Control of voltage booster for A D converter circuitNote...

Page 248: ...on mode reference voltage generator operates Note Data of the first conversion cannot be used immediately after A D conversion is started Figure 13 3 Timing Chart When Boost Reference Voltage Generato...

Page 249: ...on ADS0 is set by an 8 bit memory manipulation instruction RESET input sets the value of this register to 00H Figure 13 4 Format of Analog Input Channel Specification Register 0 ADS0 Address FF81H Aft...

Page 250: ...AR remains set If the analog input is smaller than 1 2 AVDD the MSB is reset 6 Next bit 8 of SAR is automatically set and the operation proceeds to the next comparison The series resistor string volta...

Page 251: ...ed continuously until bit 7 ADCS0 of A D converter mode register 0 ADM0 is reset 0 by software If a write operation is performed to ADM0 or analog input channel specification register 0 ADS0 during an...

Page 252: ...ADCR0 0 5 AVDD VAIN ADCR0 0 5 AVDD 1 024 1 024 where INT Function which returns integer part of value in parentheses VAIN Analog input voltage AVDD AVDD pin voltage ADCR0 A D conversion result regist...

Page 253: ...G is input A D conversion of the voltage applied to the analog input pin specified by analog input channel specification register 0 ADS0 starts Upon the end of the A D conversion the conversion result...

Page 254: ...2V0UD Figure 13 7 A D Conversion by Hardware Start When Falling Edge Is Specified Remarks 1 n 0 1 7 2 m 0 1 7 A D conversion ADCR0 ADTRG INTAD0 ADM0 set ADCE0 1 ADCS0 1 TRG0 1 ADS0 rewrite Standby sta...

Page 255: ...signal INTAD0 is generated After one A D conversion operation is started and ended the next conversion operation is immediately started A D conversion operations are repeated until new data is writte...

Page 256: ...value and the theoretical value Zero scale error full scale error integral linearity error differential linearity error and errors which are combi nations of these express overall error Furthermore qu...

Page 257: ...the conversion characteristics deviate from the ideal linear relationship It expresses the maximum value of the difference between the actual measured value and the ideal straight line when the zero...

Page 258: ...time from when the sampling is started to the time when the digital output was obtained Sampling time is included in the conversion time in the characteristics table 9 Sampling time This is the time t...

Page 259: ...the absolute maximum rating range the conversion value of that channel will be undefined and the conversion values of other channels may also be affected 3 Conflicting operations 1 Conflict between A...

Page 260: ...s may reduce the conversion resolution Also if digital pulses are applied to other analog input pins during A D conversion the expected A D conversion value may not be obtainable due to coupling noise...

Page 261: ...bit 7 ADCS0 of A D converter mode register 0 ADM0 is set to 1 without setting bit 0 ADCE0 to 1 the first value converted immediately after A D conversion has been started may not satisfy the rated val...

Page 262: ...19 Timing of Reading Conversion Result When Conversion Result Is Normal 12 Notes on board design Locate analog circuits as far away from digital circuits as possible on the board because the analog c...

Page 263: ...AVSS pins Figure 13 20 shows an example of connecting capacitors Figure 13 20 Example of Connecting Capacitor to AVDD Pin Remark C1 4 7 F to 10 F reference value C2 0 01 F to 0 1 F reference value Con...

Page 264: ...microcontroller cannot follow an analog signal with a high differential coefficient because a lowpass filter is created To convert a high speed analog signal or to convert an analog signal in scan mo...

Page 265: ...smit and receive operations are enabled in 3 wire serial I O mode the processing time for data transfers is reduced The first bit of the serially transferred 8 bit data is fixed as the MSB 3 wire seri...

Page 266: ...eive shift operations synchronized with the serial clock When 1 is set to bit 7 CSIE3 of serial operation mode register 3 CSIM3 a serial operation can be started by writing data to or reading data fro...

Page 267: ...RESET input sets the value of this register to 00H Caution In 3 wire serial I O mode set the port mode register PMXX as follows Set the output latch of a port set to output mode PMXX 0 to 0 During se...

Page 268: ...mode Transfer start trigger SO3 P21 pin function 0 Transmit transmit and receive mode Write to SIO3 SO3 1 Receive only mode Read from SIO3 P21 SCL31 SCL30 Clock selection 0 0 External clock input to S...

Page 269: ...nstruction RESET input sets the value of this register to 00H Address FFAFH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM3 CSIE3 0 0 0 0 MODE SCL31 SCL30 CSIE3 SIO3 operation enable disable specific...

Page 270: ...set by a 1 bit or 8 bit memory manipulation instruction RESET input sets the value of this register to 00H Caution In 3 wire serial I O mode set the port mode register PMXX as follows Set the output...

Page 271: ...P21 pin function 0 Transmit transmit and receive mode Write to SIO3 SO3 1 Receive only mode Read from SIO3 P21 SCL31 SCL30 Clock selection 0 0 External clock input to SCK3 0 1 fX 23 1 25 MHz 1 0 fX 2...

Page 272: ...Mode 3 Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set or read to serial I O shift register 3 SIO3 SIO3 operation control b...

Page 273: ...be shortened in the 3 wire serial I O mode because transmission and reception can be simultaneously executed in this mode In addition whether 8 bit data is transferred with the MSB or LSB first can b...

Page 274: ...OTB1 when CSOT1 1 during serial communication 2 Serial I O shift register 1 SIO1 This is an 8 bit register that converts data from parallel into serial or vice versa Reception is started by reading da...

Page 275: ...0 0 CSOT1 CSIE1 Operation control in 3 wire serial I O mode 0 Stops operation SI1 P23 SO1 P24 and SCK1 P25 pins can be used as general purpose port pins 1 Enables operation SI1 P23 SO1 P24 and SCK1 P2...

Page 276: ...0 0 1 0 1 2 1 0 3 1 1 4 CKS12 CKS11 CKS10 Transfer clock CSI1 selection 0 0 0 fX 22 2 5 MHz 0 0 1 fX 23 1 25 MHz 0 1 0 fX 24 625 kHz 0 1 1 fX 25 312 5 kHz 1 0 0 fX 26 156 25 kHz 1 0 1 fX 27 78 125 kHz...

Page 277: ...struction RESET input sets the value of this register to 00H Address FFB0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM1 CSIE1 TRMD1 0 DIR1 0 0 0 CSOT1 CSIE1 Operation control in 3 wire serial I O...

Page 278: ...ation SI1 P23 SO1 P24 and SCK1 P25 pins can be used in 3 wire serial I O mode TRMD1Note 2 Transmit receive mode selection 0Note 3 Receive mode transmission disabled 1 Transmit receive mode DIR1Note 4...

Page 279: ...0 0 0 fX 22 2 5 MHz 0 0 1 fX 23 1 25 MHz 0 1 0 fX 24 625 kHz 0 1 1 fX 25 312 5 kHz 1 0 0 fX 26 156 25 kHz 1 0 1 fX 27 78 125 kHz 1 1 0 fX 28 39 0625 kHz 1 1 1 External clock Cautions 1 When CSIE1 1 o...

Page 280: ...of port mode register 2 Cleared to 0 Bit 5 PM25 of port mode register 2 Cleared to 0 Bit 4 P24 of port 2 Cleared to 0 Bit 5 P25 of port 2 Cleared to 0 2 Receive mode with transmission disabled a To u...

Page 281: ...ister 1 CSIM1 is 0 Reception is started when data is read from serial I O shift register 1 SIO1 After communication has been started bit 0 CSOT1 of CSIM1 is set to 1 When communication of 8 bit data h...

Page 282: ...re 15 4 Timing in 3 Wire Serial I O Mode 2 2 2 Transmission reception timing Type 2 TRMD1 1 DIR1 0 CKP1 0 DAP1 1 ABH 56H ADH 5AH B5H 6AH D5H AAH 55H communication data 55H is written to SOTB1 SCK1 Rea...

Page 283: ...AP1 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK1 SO1 Writing to SOTB1 or reading from SIO1 SI1 capture CSIIF1 CSOT1 D7 D6 D5 D4 D3 D2 D1 D0 SCK1 SO1 Writing to SOTB1 or reading from SIO1 SI1 capture CSIIF1 CSOT1 D7...

Page 284: ...same time the first bit of the receive data is stored in the SIO1 register via the SI1 pin The second and subsequent bits are latched to the output latch from SIO1 at the next falling or rising edge...

Page 285: ...put value of the last bit Figure 15 7 Output Value of SO1 Pin Last Bit 1 Type 1 CKP1 0 and DAP1 0 or CKP1 1 DAP1 0 2 Type 2 CKP1 0 and DAP1 1 or CKP1 1 DAP1 1 Last bit Next request is issued SCK1 SOTB...

Page 286: ...2 Asynchronous serial interface UART mode fixed to LSB first This mode enables full duplex operation wherein one byte of data after the start bit is transmitted and received The on chip baud rate gene...

Page 287: ...xD0 P26 TxD0 P27 PE0 FE0 OVE0 Asynchronous serial interface status register 0 ASIS0 INTSER0 INTST0 Baud rate generatorNote fX 2 to fX 27 TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 Asynchronous serial interface...

Page 288: ...igned to TXS0 and receive buffer register 0 RXB0 A read operation reads values from RXB0 2 Receive shift register 0 RX0 This register converts serial data input via the RxD0 pin to parallel data When...

Page 289: ...s serial interface mode register 0 ASIM0 Asynchronous serial interface status register 0 ASIS0 Baud rate generator control register 0 BRGC0 1 Asynchronous serial interface mode register 0 ASIM0 This i...

Page 290: ...1 1 UART mode Serial function RxD0 transmit and receive PS01 PS00 Parity bit specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity e...

Page 291: ...framing error 1 Framing errorNote 1 Stop bit not detected OVE0 Overrun error flag 0 No overrun error 1 Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer...

Page 292: ...1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0 0 1 fSCK 25 9 1 0 1 0 fSCK 26 10 1 0 1 1 fSCK 27 11 1 1 0...

Page 293: ...ster 0 ASIM0 ASIM0 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets the value of this register to 00H Address FFA0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ASIM0 TXE0 RXE...

Page 294: ...ings are performed by asynchronous serial interface mode register 0 ASIM0 asynchronous serial interface status register 0 ASIS0 and baud rate generator control register 0 BRGC0 a Asynchronous serial i...

Page 295: ...ransmit and receive PS01 PS00 Parity bit specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1...

Page 296: ...parity not matched FE0 Framing error flag 0 No framing error 1 Framing errorNote 1 Stop bit not detected OVE0 Overrun error flag 0 No overrun error 1 Overrun errorNote 2 Next receive operation was co...

Page 297: ...ut clock selection for baud rate generator k 0 0 0 0 fSCK 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSC...

Page 298: ...oscillation frequency n Value set via TPS00 to TPS02 1 n 7 For details see Table 16 2 k Value set via MDL00 to MDL03 0 k 14 Table 16 2 shows the relationship between the 5 bit counter s source clock a...

Page 299: ...0 00 38 400 30H 1 73 30H 0 00 2BH 1 10 2AH 0 16 76 800 20H 1 73 20H 0 00 1BH 1 10 1AH 0 16 115 200 16H 1 36 16H 3 03 12H 1 10 11H 2 12 153 600 10H 1 73 10H 0 00 Baud Rate fX 7 3728 MHz fX 5 MHz fX 4 1...

Page 300: ...ud rate error tolerance range Figure 16 6 Baud Rate Error Tolerance When k 0 Including Sampling Errors Basic timing START D0 D7 P STOP High speed limit timing START D0 D7 P STOP Low speed limit timing...

Page 301: ...y zero parity or no parity Stop bit s 1 bit or 2 bits Asynchronous serial interface mode register 0 ASIM0 is used to set the character bit length parity selection and stop bit length within each data...

Page 302: ...data that include a parity bit and a parity error occurs when the counted result is an odd number ii Odd parity During transmission The number of character bits in transmit data that includes a parity...

Page 303: ...S0 after which a transmit completion interrupt request INTST0 is issued The timing of the transmit completion interrupt request is shown in Figure 16 8 Figure 16 8 Timing of Asynchronous Serial Interf...

Page 304: ...the character data parity bit and one bit stop bit are detected at which point reception of one data frame is completed Once reception of one data frame is completed the receive data in the shift regi...

Page 305: ...ASIS0 Value Parity error Specified parity does not match parity of receive data 04H Framing error Stop bit was not detected 02H Overrun error Reception of the next data was completed before data was r...

Page 306: ...mode multimaster supported This mode is used for 8 bit data transfers with several devices via two lines a serial clock SCL0 line and a serial data bus SDA0 line This mode complies with the I2C bus fo...

Page 307: ...0 IIC0 SO0 latch IICE0 D SET CLEAR Q CL00 SDA0 P31 SCL0 P30 N ch open drain output Data hold time correction circuit ACK detector Wakeup controller ACK detector Stop condition detector Serial clock c...

Page 308: ...ows a serial bus configuration example Figure 17 2 Serial Bus Configuration Example Using I2 C Bus SDA0 SCL0 SDA0 VDD0 VDD0 SCL0 SDA0 SCL0 Slave CPU3 Address 2 SDA0 SCL0 Slave IC Address 3 SDA0 SCL0 S...

Page 309: ...mission and reception Write and read operations to IIC0 are used to control the actual transmit and receive operations IIC0 is set by an 8 bit memory manipulation instruction RESET input sets IIC0 to...

Page 310: ...ock 9 Serial clock wait controller This circuit controls the wait timing 10 ACK output circuit stop condition detector start condition detector and ACK detector These circuits are used to output and d...

Page 311: ...e standby mode following exit from communications remains in effect until the following communications entry conditions are met After a stop condition is detected restart is in master mode An address...

Page 312: ...ontrol 0 Disable acknowledge 1 Enable acknowledge During the ninth clock period the SDA0 line is set to low level However the ACK is invalid during address transfers and is valid when EXC0 1 Condition...

Page 313: ...stop condition will be generated during the high level period of the ninth clock When a ninth clock must be output WTIM0 should be changed from 0 to 1 during the wait period following output of eight...

Page 314: ...is input ALD0 Detection of arbitration loss 0 This status means either that there was no arbitration or that the arbitration result was a win 1 This status indicates the arbitration result was a loss...

Page 315: ...n a stop condition is detected When a start condition is generated Cleared by LREL0 1 Slave When IICE0 changes from 1 to 0 When 1 is input by the first byte s LSB Cleared by WREL0 1Note transfer direc...

Page 316: ...the next byte s first clock following address transfer Cleared by LREL0 1 When IICE0 changes from 1 to 0 When RESET is input SPD0 Detection of stop condition 0 Stop condition was not detected 1 Stop...

Page 317: ...is at low level When the SCL0 line is at high level When IICE0 0 When RESET is input DAD0 Detection of SDA0 line level valid only when IICE0 1 0 SDA0 line was detected at low level 1 SDA0 line was det...

Page 318: ...lation frequency 3 Figures in parentheses are for operation with fX 8 38 MHz 4 IIC function expansion register 0 IICX0 This register is used to set the function expansion for the I2 C bus IICX0 is set...

Page 319: ...and slave devices Input is Schmitt input 2 SDA0 This pin is used for serial data input and output This pin is an N ch open drain output for both master and slave devices Input is Schmitt input Since...

Page 320: ...master or slave device normally it is output by the device that receives 8 bit data The serial clock SCL0 is continuously output by the master device However in the slave device the SCL0 s low level...

Page 321: ...ot issued if data other than a local address or extension code is received during slave device operation The slave address and the eighth bit which specifies the transfer direction as described in 17...

Page 322: ...ion of the eighth bit following the 7 address data bits causes bit 3 TRC0 of the IIC status register 0 IICS0 to be set When this TRC0 bit s value is 0 it indicates receive mode Therefore ACKE0 should...

Page 323: ...tion is a signal that the master device outputs to the slave device when serial transfer has been completed The slave device includes hardware that detects stop conditions Figure 17 13 Stop Condition...

Page 324: ...led for both the master and slave devices the next data transfer can begin Figure 17 14 Wait Signal 1 2 1 When master device has a nine clock wait and slave device has an eight clock wait master trans...

Page 325: ...rding to previously set ACKE0 value Transfer lines Wait signal from master and slave Wait signal from slave Remark ACKE0 Bit 2 of IIC control register 0 IICC0 WREL0 Bit 5 of IIC control register 0 IIC...

Page 326: ...ta Stop normal transmission reception i When WTIM0 0 SPT0 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICS0 1000 110B 2 IICS0 1000 000B 3 IICS0 1000 000B Sets WTIM0 4 IICS0 1000 00B S...

Page 327: ...0 000B Sets WTIM0 3 IICS0 1000 00B Clears WTIM0 sets STT0 4 IICS0 1000 110B 5 IICS0 1000 000B Sets WTIM0 6 IICS0 1000 00B Sets SPT0 7 IICS0 00000001B Remark Always generated Generated only when SPIE0...

Page 328: ...D0 AK SP 1 2 3 4 5 1 IICS0 1010 110B 2 IICS0 1010 000B 3 IICS0 1010 000B Sets WTIM0 4 IICS0 1010 00B Sets SPT0 5 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When...

Page 329: ...When WTIM0 0 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 0001 000B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t ca...

Page 330: ...D0 AK SP 1 2 3 4 5 1 IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 0001 110B 4 IICS0 0001 000B 5 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restar...

Page 331: ...2 3 4 5 1 IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 0010 010B 4 IICS0 0010 000B 5 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart extension...

Page 332: ...to AD0 RW AK D7 to D0 AK SP 1 2 3 4 1 IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 00000 10B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restar...

Page 333: ...AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS0 0010 010B 2 IICS0 0010 000B 3 IICS0 0010 000B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST...

Page 334: ...2 3 4 5 1 IICS0 0010 010B 2 IICS0 0010 000B 3 IICS0 0001 110B 4 IICS0 0001 000B 5 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart matches w...

Page 335: ...CS0 0010 010B 2 IICS0 0010 000B 3 IICS0 0010 010B 4 IICS0 0010 000B 5 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart extension code recept...

Page 336: ...00 10B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart does not match with address not extension code ST AD6 to AD0 RW AK D7 to D0 AK ST...

Page 337: ...to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS0 0101 110B Example When ALD0 is read during interrupt servicing 2 IICS0 0001 000B 3 IICS0 0001 000B 4 IICS0 00000001B Remark Always generated Generated only whe...

Page 338: ...10B Example When ALD0 is read during interrupt servicing 2 IICS0 0010 000B 3 IICS0 0010 000B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to...

Page 339: ...RW AK D7 to D0 AK D7 to D0 AK SP 1 2 1 IICS0 01000110B Example When ALD0 is read during interrupt servicing 2 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 b When arbitration los...

Page 340: ...D0 AK SP 1 2 3 1 IICS0 10001110B 2 IICS0 01000000B Example When ALD0 is read during interrupt servicing 3 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 ii When WTIM0 1 ST AD6 to...

Page 341: ...1 2 3 1 IICS0 1000 110B 2 IICS0 01000110B Example When ALD0 is read during interrupt servicing 3 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care n 6 to 0 ii Extension c...

Page 342: ...generated Generated only when SPIE0 1 Don t care n 6 to 0 f When arbitration loss occurs due to low level data when attempting to generate a restart condition i When WTIM0 1 ST AD6 to AD0 RW AK D7 to...

Page 343: ...00B Sets STT0 3 IICS0 01000001B Remark Always generated Generated only when SPIE0 1 Don t care h When arbitration loss occurs due to low level data when attempting to generate a stop condition i When...

Page 344: ...f slave address register 0 SVA0 and an extension code has not received neither INTIIC0 nor a wait occurs Remark The numbers in the table indicate the number of the serial clock s clock signals Interru...

Page 345: ...the extension code reception flag EXC0 is set for extension code reception and an interrupt request INTIIC0 is issued at the falling edge of the eighth clock The local address stored in slave address...

Page 346: ...status register 0 IICS0 is set 1 at the timing at which the arbitration loss occurred and the SCL0 and SDA0 lines are both set to high impedance which releases the bus The arbitration loss is detecte...

Page 347: ...lowing byte transferNote 1 stop condition When SCL0 is at low level while attempting to output a restart condition Notes 1 When WTIM0 bit 3 of IIC control register 0 IICC0 1 an interrupt request occur...

Page 348: ...tion is detected When the bus release is detected when a stop condition is detected writing to IIC shift register 0 IIC0 causes the master s address transfer to start At this point IICC0 s bit 4 SPIE0...

Page 349: ...ift register 0 STT0 Bit 1 of IIC control register 0 IICC0 STD0 Bit 1 of IIC status register 0 IICS0 SPD0 Bit 0 of IIC status register 0 IICS0 Communication reservations are accepted at the following t...

Page 350: ...s then perform master device communication When using multiple masters it is not possible to perform master device communication when the bus has not been released when a stop condition has not been d...

Page 351: ...er clock IICC0 H IICE0 SPIE0 WTIM0 1 STT0 1 Start IIC0 write transfer Start IIC0 write transfer WREL0 1 Start reception Generate restart condition or stop condition START Data processing Data processi...

Page 352: ...n Flowchart IICC0 H IICE0 1 WREL0 1 Start reception Detect restart condition or stop condition START ACKE0 0 WREL0 1 Data processing Data processing LREL0 1 No Yes No No No No No No No Yes No Yes Yes...

Page 353: ...device transmits the TRC0 bit bit 3 of IIC status register 0 IICS0 that specifies the data transfer direction and then starts serial communication with the slave device Figures 17 21 and 17 22 show t...

Page 354: ...To cancel slave wait write FFH to IIC0 or set WREL0 IIC0 ACKD0 STD0 SPD0 WTIM0 H H L L L L H H H L L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 IN...

Page 355: ...l slave wait write FFH to IIC0 or set WREL0 IIC0 ACKD0 STD0 SPD0 WTIM0 H H L L L L L L H H H H L L L L L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0...

Page 356: ...write FFH to IIC0 or set WREL0 IIC0 ACKD0 STD0 SPD0 WTIM0 H H L L L L H H H L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Pr...

Page 357: ...address Note To cancel master wait write FFH to IIC0 or set WREL0 IIC0 ACKD0 STD0 SPD0 WTIM0 H H L L H H L ACKE0 MSTS0 STT0 L L SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT...

Page 358: ...ter wait write FFH to IIC0 or set WREL0 IIC0 ACKD0 STD0 SPD0 WTIM0 H H H L L L L L L H H H L L L L L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INT...

Page 359: ...cancel master wait write FFH to IIC0 or set WREL0 IIC0 ACKD0 STD0 SPD0 WTIM0 H H L L L H ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 S...

Page 360: ...de 5 Simultaneous driving of static display up to 12 segments and dynamic display The operation mode of the alternate function pins S0 to S11 can be switched between the static display mode and dynami...

Page 361: ...ments 4 commons 18 2 LCD Controller Driver Configuration The LCD controller driver consists of the following hardware Table 18 3 LCD Controller Driver Configuration Item Configuration Display output S...

Page 362: ...REG0 to 3 SEGREG12 to 15 SEGREG16 to 19 SEGREG36 to 39 SEGREG39 SEGREG2 SEGREG1 SEGREG0 4 bits 4 bits Segment driver SDSEL 30 4 bits 4 bits 4 bits 4 bits SDSEL 31 SDSEL 32 Segment driver 0 S0 to S3 Se...

Page 363: ...clock control register 3 LCDC3 LCD gain adjust register 0 VLCG0 Static dynamic display switching register 3 SDSEL3 Pin function switching registers PF8 to PF11 1 LCD display mode register 3 LCDM3 This...

Page 364: ...BLONNote 2 Blinking display control 0 Blinking display OFF 1Note 3 Blinking display ON LCDM0Note 4 Dynamic static display alternate pinsNotes 5 6 Dynamic pin Time division Bias mode Time division Bias...

Page 365: ...n GND output mode 3 Clear VLCON to 0 The LCD booster circuit stops 2 The blinking cycle is generated using the interval time of the watch timer 0 5 s at 32 768 kHz When the blinking function is not us...

Page 366: ...rence clock generating frame frequency 0 0 fLCD 26 0 1 fLCD 27 1 0 fLCD 28 1 1 fLCD 29 Caution Do not rewrite LCDC3 while the LCD is operating Be sure to set this bit while LCDON 0 SCOC 0 and VLCON 0...

Page 367: ...LCG0 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets the value of this register to 00H Figure 18 6 Format of LCD Gain Adjust Register 0 VLCG0 Symbol 7 6 5 4 3 2 1 0 Address...

Page 368: ...c Dynamic Display Switching Register 3 SDSEL3 Address FF92H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 SDSEL3 0 0 0 0 0 SDSEL32 SDSEL31 SDSEL30 SDSEL32 SDSEL31 SDSEL30 Number of segments Number of seg...

Page 369: ...F87 PF86 PF85 PF84 PF83 PF82 PF81 PF80 Address FF59H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PF9 PF97 PF96 PF95 PF94 PF93 PF92 PF91 PF90 Address FF5AH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PF1...

Page 370: ...ink and 1 to bit 3 BLON of LCD display mode register 3 LCDM3 In this case however the display data of the corresponding segment must be 1 Figure 18 9 shows the relationship between the LCD display dat...

Page 371: ...display mode using bit 0 LCDM0 of LCD display mode register 3 LCDM3 5 Select the source clock and frame frequency of the LCD using LCD clock control register 3 LCDC3 6 Select the LCD reference voltage...

Page 372: ...ory are read in synchronization with the SCOM0 COM0 COM1 COM2 and COM3 timing respectively and if the value of the bit is 1 it is converted to the selection voltage If the value of the bit is 0 it is...

Page 373: ...LCD ON voltage is only produced when the common signal and segment signal are both at the selection voltage other combinations produce the OFF voltage Figure 18 10 Common Signal Waveform a Static disp...

Page 374: ...s and Phases a Static display mode Remark T One LCDCL cycle b Dynamic display mode 1 3 bias method Remark T One LCDCL cycle Selected Not selected Common signal Segment signal VLCD0 VSS VLCD VLCD0 VSS...

Page 375: ...alue 0 47 F is required because a capacitance division method is employed to generate the supply voltage to drive the LCD Table 18 6 Output Voltages of VLC0 to VLC2 Pins VLCG0 GAIN 0 GAIN 1 LCD Drivin...

Page 376: ...mon signal timing At this time set the SDSEL3 register to 03H to set the S0 to S7 pins to the static display mode Table 18 7 Selection and Non Selection Voltages SCOM0 Segment S0 S1 S2 S3 S4 S5 S6 S7...

Page 377: ...DRIVER User s Manual U15798EJ2V0UD Figure 18 14 Static LCD Panel Connection Example SDSEL3n 1 n 0 1 Timing strobe SCOM0 BIT0 BIT1 BIT2 BIT3 S0 S1 S2 S3 0 FA00H 1 1 0 2 1 3 S4 S5 S6 S7 1 4 1 5 0 6 1 7...

Page 378: ...ONTROLLER DRIVER User s Manual U15798EJ2V0UD Figure 18 15 Static LCD Drive Waveform Examples TF VLCD0 VSS0 SCOM0 VLCD0 VSS0 S1 VLCD0 VSS0 S2 VLCD 0 Non display waveform SCOM0 S2 VLCD VLCD 0 Display wa...

Page 379: ...tput to pins S21 to S23 as shown in Table 18 8 at the COM0 to COM2 common signal timings Table 18 8 Selection and Non Selection Voltages COM0 to COM2 Segment S21 S22 S23 Common COM0 NS S S COM1 S S S...

Page 380: ...1 1 1 0 2 1 0 3 S4 S5 S6 S7 1 1 4 0 5 1 0 6 0 0 7 S8 S9 S10 S11 0 8 1 0 9 1 1 A 1 B S12 S13 S14 S15 1 0 C 1 0 D 1 E 1 0 F S16 S17 S18 S19 1 1 FA10H 1 1 1 0 2 1 0 3 S20 S21 S22 S23 1 4 0 1 5 1 1 6 1 7...

Page 381: ...Time Division LCD Drive Waveform Examples 1 3 Bias Method VLCD0 VLCD2 COM0 VLCD 0 COM0 S21 VLCD VLCD1 1 3VLCD 1 3VLCD VSS VLCD0 VLCD2 COM1 VLCD1 VSS VLCD0 VLCD2 COM2 VLCD1 VSS VLCD0 VLCD2 S21 VLCD1 V...

Page 382: ...non selection voltages must be output to pins S28 and S29 as shown in Table 18 9 at the COM0 to COM3 common signal timings Table 18 9 Selection and Non Selection Voltages COM0 to COM3 Segment S28 S29...

Page 383: ...0 S11 1 1 0 8 1 1 1 9 1 1 0 A 1 0 1 B S12 S13 S14 S15 0 1 0 C 1 0 0 D 1 1 0 E 0 0 1 F S16 S17 S18 S19 1 0 0 FA10H 0 1 1 1 0 1 0 2 0 0 0 3 S20 S21 S22 S23 1 1 0 4 1 1 1 5 1 1 0 6 1 0 0 7 S24 S25 S26 S2...

Page 384: ...Waveform Examples 1 3 Bias Method Remark The waveforms of COM2 S28 and COM3 S28 are omitted TF VLCD0 VLCD2 COM0 VLCD 0 COM0 S28 VLCD VLCD1 1 3VLCD 1 3VLCD VSS VLCD0 VLCD2 COM1 VLCD1 VSS VLCD0 VLCD2 C...

Page 385: ...5798EJ2V0UD 18 8 4 Simultaneous driving of static display and dynamic display Simultaneous driving of static display S0 to S11 and dynamic display is possible with the PD780344 780354 780344Y 780354Y...

Page 386: ...group by setting the priority specification flag registers PR0L PR0H PR1L High priority interrupt nesting can be applied to low priority interrupts If two or more interrupts with the same priority ar...

Page 387: ...nterface IIC0 transfer 0020H PD780344Y 780354Y Subseries only Note 3 15 INTWTNI0 Reference time interval signal from watch timer 0022H 16 INTTM00 Match between TM00 and CR00 0024H when CR00 is specifi...

Page 388: ...address generator Standby release signal B Internal maskable interrupt Internal bus Interrupt request IF MK IE PR ISP Priority controller Vector table address generator Standby release signal C Extern...

Page 389: ...terrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specification flag MEM Memory expansion mode register IF MK IE PR ISP Internal bus Interru...

Page 390: ...Flag Interrupt Mask Flag Priority Specification Flag Register Register Register INTWDT WDTIFNote 1 IF0L WDTMKNote 1 MK0L WDTPRNote 1 PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2...

Page 391: ...4 3 2 1 0 IF0L PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 WDTIF Address FFE1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0H WTNIIF0 IICIF0Note CSIIF3 CSIIF1 STIF0 SRIF0 SERIF0 KRIF Address FFE2H After reset...

Page 392: ...PMK3 PMK2 PMK1 PMK0 WDTMK Address FFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H WTNIMK0 IICMK0Note CSIMK3 CSIMK1 STMK0 SRMK0 SERMK0 KRMK Address FFE6H After reset FFH R W Symbol 7 6 5 4 3 2 1...

Page 393: ...es of these registers to FFH Figure 19 4 Format of Priority Specification Flag Registers PR0L PR0H PR1L Address FFE8H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L PPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0...

Page 394: ...ising Edge Enable Register EGP External Interrupt Falling Edge Enable Register EGN Address FF48H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGP 0 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 Address FF49H After...

Page 395: ...and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag The PSW cont...

Page 396: ...on maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI instruction execution and one main rout...

Page 397: ...control register not accessed Interval timer No Reset processing No Interrupt request generation Start of interrupt servicing Interrupt request held pending No No No Yes Yes Yes Yes Yes WDTM Watchdog...

Page 398: ...e interrupt servicing program execution Main routine NMI request 1 Execution of 1 instruction NMI request 2 Execution of NMI request 1 NMI request 2 held pending Servicing of pending NMI request 2 Mai...

Page 399: ...e Interrupt Until Servicing Minimum Time Maximum TimeNote When PR 0 7 clocks 32 clocks When PR 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait...

Page 400: ...held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Vectored interrupt servicing Any high priority interrupt reques...

Page 401: ...contents are saved into the stacks in the order of the program status word PSW then program counter PC the IE flag is reset 0 and the contents of the vector table 003EH 003FH are loaded into the PC a...

Page 402: ...y being serviced is generated during interrupt servicing it is not acknowledged for nesting Interrupt requests that are not enabled because of the interrupt disable state or they have a lower priority...

Page 403: ...INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx and nesting does not take place The INTyy interrupt request is held pending and is...

Page 404: ...struction is not issued therefore interrupt request INTyy is not acknowledged and nesting does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one...

Page 405: ...R0H and PR1L registers Caution The BRK instruction is not one of the above listed interrupt request hold instructions However the software interrupt activated by executing the BRK instruction causes t...

Page 406: ...use this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is required to secure the oscillation stabilization time after the...

Page 407: ...R W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection 0 0 0 212 fX 410 s 0 0 1 214 fX 1 64 ms 0 1 0 215 fX 3 28 ms 0 1 1 216 fX 6 55 ms...

Page 408: ...ration stops multiplication circuit 16 bit timer event Operable Operation stops counter 0 8 bit timer A0 Operable Operable when INTTMB0 carrier clock and timer B0 are selected as count clock 8 bit tim...

Page 409: ...Wait Wait Operation mode HALT mode Operation mode Oscillation Clock Standby release signal Interrupt request Remarks 1 The broken line indicates the case when the interrupt request which has released...

Page 410: ...2 Values in parentheses are for operation with fX 10 MHz Table 20 2 Operation After HALT Mode Release Release Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction ex...

Page 411: ...8F0354 78F0354Y Only Clock Status Release Condition NOP Instruction Setting One Instruction Subclock multiplied by 4 HALT mode during main RESET input Unnecessary is used processing Interrupt HALT mod...

Page 412: ...ating Statuses STOP Mode Setting With Subsystem Clock Without Subsystem Clock Item Clock generator Only main system clock oscillation is stopped CPU Operation stops Port output latch Status before STO...

Page 413: ...stabilization time vectored interrupt service is carried out If interrupt acknowledge is disabled the next address instruction is executed Figure 20 4 STOP Mode Release by Interrupt Request Generatio...

Page 414: ...Operation mode STOP mode Operation mode Oscillation stop Clock RESET signal Oscillation Oscillation Reset period Remarks 1 fX Main system clock oscillation frequency 2 Values in parentheses are for o...

Page 415: ...e just after reset release When a high level is input to the RESET pin the reset is released and program execution starts after the lapse of oscillation stabilization time 217 fX The reset applied by...

Page 416: ...et Due to Watchdog Timer Overflow Hi Z Normal operation Reset period Oscillation stop Oscillation stabilization time wait Normal operation Reset processing X1 Watchdog timer overflow Internal reset si...

Page 417: ...rescaler mode register 0 PRM0 00H Mode control register 0 TMC0 00H Capture compare control register 0 CRC0 00H Output control register 0 TOC0 00H 8 bit timer event counters A0 B0 Timer counters TMA0 T...

Page 418: ...ASIM0 00H Asynchronous serial interface status register 0 ASIS0 00H Baud rate generator control register 0 BRGC0 00H Transmit shift register 0 TXS0 FFH Receive buffer register 0 RXB0 Serial interface...

Page 419: ...on chip flash memory program Caution ROM correction cannot be emulated by the in circuit emulator IE 78K0 NS IE 78K0 NS A 22 2 ROM Correction Configuration ROM correction consists of the following har...

Page 420: ...rection Address Registers 0 and 1 Cautions 1 Set the CORAD0 and CORAD1 when bit 1 COREN0 and bit 3 COREN1 of the correction control register CORCN are 0 2 Only start addresses where operation codes ar...

Page 421: ...are matched CORCN is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets the value of this register to 00H Figure 22 3 Format of Correction Control Register CORCN Address FF8AH A...

Page 422: ...troller When two places should be corrected store the branch destination judgment program as well The branch destination judgment program checks which one of the addresses set to correction address re...

Page 423: ...the internal expansion RAM in the main program 5 After the main program is started the fetch address value and the values set in CORAD0 and CORAD1 are always compared by the comparator in the ROM corr...

Page 424: ...D Figure 22 6 ROM Correction Operation No Yes Internal ROM on chip flash memory program start Does fetch address match with correction address Set correction status flag Correction branch branch to ad...

Page 425: ...0 1 CORAD0 CORAD1 matches the fetch address value after the main program is started 2 Branches to any address address F702H in this example by setting the entire space branch instruction BR addr16 to...

Page 426: ...anches to address F7FDH when fetch address matches correction address 2 Branches to correction program 3 Returns to internal ROM program on chip flash memory Caution Do not use internal high speed RAM...

Page 427: ...ches correction address 6 Branches to branch destination judgment program 7 Branches to correction program 2 by branch destination judgment program BTCLR CORST1 yyyyH 8 Returns to internal ROM on chip...

Page 428: ...rom the set address value 3 Do not set the address value of instruction immediately after the instruction that sets the correction enable flag COREN0 COREN1 to 1 to correction address register 0 or 1...

Page 429: ...h memory with the memory mounted on the target system on board To do this connect the dedicated flash programmer to the target system Using flash memory in a development environment or application ena...

Page 430: ...up resistors of pins P70 to Not provided On chip pull up resistor can be specified by mask option in P73 1 bit units A D converter resolution 10 bits 8 bits 10 bits 8 bits 10 bits Serial interface II...

Page 431: ...to C8H 46H or 48H after reset Figure 23 1 Format of Memory Size Switching Register IMS Address FFF0H After reset CFH R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0...

Page 432: ...this register to 0CH Caution Be sure to set IXS to 0BH as the initial setting of the program Reset input initializes IXS to 0CH Be sure to set IXS to 0BH after reset Set the mask ROM versions in the s...

Page 433: ...is solder mounted on the target system Distinguishing software facilities low quantity varied model production Easy data adjustment when starting mass production 23 3 1 Programming environment The fol...

Page 434: ...4 to Optional 1 to 10 MHz 1 0 SI1 P23 1 CSI1 SIO ch 1 625 kHzNote Note 2 SO1 P24 100 Hz to 2 SCK1 P25 MHz Note 2 UART UART ch0 4 800 to Optional 1 to 10 MHz 1 0 RxD0 P26 8 UART0 UART ch 0 76 800 bps N...

Page 435: ...3 HS CLKNote X1 VSS0 VSS1 AVSS PD78F0354 78F0354Y c 3 wire serial I O CSI1 Dedicated flash programmer VPP VDD RESET SCK SO TxD SI RxD CLKNote GND VPP VDD0 VDD1 AVDD RESET SCK1 SI1 SO1 X1 VSS0 VSS1 AVS...

Page 436: ...upply voltage before starting programming If Flashpro III Flashpro IV is used as a dedicated flash programmer the following signals are generated for the PD78F0354 78F0354Y For details refer to the ma...

Page 437: ...to the VPP pin 2 Use the jumper on the board to switch the VPP pin input to either the programmer or directly to GND A VPP pin connection example is shown below Figure 23 6 VPP Pin Connection Example...

Page 438: ...operation of other device If the dedicated flash programmer output or input is connected to a serial interface pin input or output that is connected to another device input a signal is output to the d...

Page 439: ...that communicate with the flash programmer are in the same status as immediately after reset If the external device does not recognize initial statuses such as the output high impedance status theref...

Page 440: ...sh Writing Adapter with 3 Wire Serial I O SIO3 PD78F0354 PD78F0354Y GND SI SO SCK CLKOUT RESET VPP RESERVE HS VDD VPP2 LVDD WRITER INTERFACE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23...

Page 441: ...SI SO SCK CLKOUT RESET VPP RESERVE HS VDD VPP2 LVDD WRITER INTERFACE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80...

Page 442: ...SCK CLKOUT RESET VPP RESERVE HS VDD VPP2 LVDD WRITER INTERFACE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 7...

Page 443: ...KOUT RESET VPP RESERVE HS VDD VPP2 LVDD WRITER INTERFACE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 2...

Page 444: ...ON SET This chapter lists each instruction set of the PD780344 780354 780344Y 780354Y Subseries in table form For details of each instruction s operation and operation code refer to the separate docum...

Page 445: ...C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for specification Table 24 1 Operand Identifiers and Specification Methods Identifier Specification Method r X...

Page 446: ...Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in...

Page 447: ...yte 2 8 9 A HL byte HL byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C HL C A 1 6 7 HL C A XCH A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8...

Page 448: ...A HL byte 2 8 9 A CY A HL byte A HL B 2 8 9 A CY A HL B A HL C 2 8 9 A CY A HL C ADDC A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY...

Page 449: ...A CY A addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY A HL C 2 8 9 A CY A HL C CY AND A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3...

Page 450: ...addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B A HL C 2 8 9 A A HL C CMP A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr...

Page 451: ...A3 0 HL 7 4 HL 3 0 ADJBA 2 4 Decimal Adjust Accumulator after Addition ADJBS 2 4 Decimal Adjust Accumulator after Subtract MOV1 CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4...

Page 452: ...CY PSW bit 3 7 CY CY PSW bit CY HL bit 2 6 7 CY CY HL bit SET1 saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 HL bit 2 6 8 HL bit 1 CLR1 saddr bit 2 4 6 sad...

Page 453: ...SP 1 PCL SP R R R PSW SP 2 SP SP 3 PUSH PSW 1 2 SP 1 PSW SP SP 1 rp 1 4 SP 1 rpH SP 2 rpL SP SP 2 POP PSW 1 2 PSW SP SP SP 1 R R R rp 1 4 rpH SP 1 rpL SP SP SP 2 MOVW SP word 4 10 SP word SP AX 2 8 SP...

Page 454: ...sp8 if sfr bit 1 then reset sfr bit A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 4 12 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit HL bit addr16 3 10 12 PC PC 3 jdisp8...

Page 455: ...4 INSTRUCTION SET User s Manual U15798EJ2V0UD 24 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 P...

Page 456: ...SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r...

Page 457: ...MOVW addr16 MOVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16...

Page 458: ...ructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand AX addr16 addr11 addr5 addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction...

Page 459: ...3 Total for P00 to P07 P20 to P27 P30 to P35 P40 to P43 15 mA Output current low IOL Per pin for P00 to P07 P20 to P27 P32 to P35 P40 to 20 mA P43 P80 to P87 P90 to P97 P100 to P107 P110 to P113 Per p...

Page 460: ...ory is written When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower limit value 1 8 V of the operating voltage range see a in the figure below When supply voltage...

Page 461: ...release Cautions 1 When using the main system clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep th...

Page 462: ...rent flows Always make the ground point of the oscillator capacitor the same potential as VSS1 Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals f...

Page 463: ...P30 P31 N ch open drain 2 7 V VDD 5 5 V 0 7VDD 5 5 V 1 8 V VDD 2 7 V 0 8VDD 5 5 V P70 to P73 N ch open drain 2 7 V VDD 5 5 V 0 7VDD 12 V 1 8 V VDD 2 7 V 0 8VDD 12 V VIH4 X1 X2 2 7 V VDD 5 5 V VDD 0 5...

Page 464: ...to P113 RESET ILIH2 X1 X2 XT1 XT2 20 A ILIH3 VIN 5 5 V P30 P31 3 A VIN 12 V P70 to P73 10 A Input leakage ILIL1 VIN 0 V P00 to P03 P10 to P17 P20 to P27 P32 to 3 A current low P35 P40 to P43 P80 to P...

Page 465: ...VDD 5 0 V 10 When LCD stoppedNote 6 25 45 A oscillation HALT Only when LCD boost function is 27 51 A modeNote 5 operatingNotes 7 9 When LCD is operatingNotes 8 9 30 60 A VDD 3 0 V 10 When LCD stopped...

Page 466: ...D 5 0 V 10 When LCD stoppedNote 6 25 45 A oscillation HALT Only when LCD boost function is 27 51 A modeNote 5 operatingNotes 7 9 When LCD is operatingNotes 8 9 30 60 A VDD 3 0 V 10 When LCD stoppedNot...

Page 467: ...fsam s 0 5Note 2 TMIB0 input fTIB 2 7 V VDD 5 5 V 0 4 MHz frequency 1 8 V VDD 2 7 V 0 275 kHz TMIB0 input high tTIHB 2 7 V VDD 5 5 V 125 ns low level width tTILB 1 8 V VDD 2 7 V 1 8 s TI50 TI51 input...

Page 468: ...50 ns 1 8 V VDD 2 7 V 300 ns SI3 hold time tKSI1 400 ns from SCK3 Delay time from tKSO1 C 100 pFNote 300 ns SCK3 to SO3 output Note C is the load capacitance of the SCK3 and SO3 output lines b SIO3 3...

Page 469: ...is the load capacitance of the SCK1 and SO1 output lines d CSI1 3 wire serial I O mode SCK1 external clock input Parameter Symbol Conditions MIN TYP MAX Unit SCK1 cycle time tKCY4 4 5 V VDD 5 5 V 200...

Page 470: ...Cb 400 400 pF Spike pulse width controlled by input filter tSP 0 50 ns Notes 1 On the start condition the first clock pulse is generated after the hold period 2 To fulfill the undefined area of the S...

Page 471: ...AC timing test points excluding X1 XT1 input 0 8VDD 0 2VDD Test points 0 8VDD 0 2VDD Clock timing X1 input VIH4 MIN VIL4 MAX 1 fX tXL tXH XT1 input VIH5 MIN VIL5 MAX 1 fXT tXTL tXTH TI timing TM00 TI...

Page 472: ...472 CHAPTER 25 ELECTRICAL SPECIFICATIONS User s Manual U15798EJ2V0UD Interrupt request input timing INTP0 to INTP6 tINTL tINTH RESET input timing RESET tRSL...

Page 473: ...ng 3 wire serial I O mode SIO3 CSI1 SI1 SI3 SO1 SO3 tKCYn tKLn tKHn tSIKn tKSIn Input data tKSOn Output data SCK1 SCK3 n 1 to 4 I2C bus mode SCL0 SDA0 Stop condition Stop condition Restart condition S...

Page 474: ...to 5 5 V AVSS VSS 0 V Parameter Symbol Conditions MIN TYP MAX Unit Resolution 10 10 10 bit Overall errorNote 4 5 V AVDD 5 5 V 0 2 0 4 FSR 2 7 V AVDD 4 5 V 0 3 0 6 FSR 2 2 V AVDD 2 7 V 0 6 1 2 FSR Con...

Page 475: ...1 tVAWAIT Gain 1 4 5 V VDD 5 5 V 4 s 1 8 V VDD 4 5 V 0 5 s Gain 1 5 1 8 V VDD 5 5 V 0 5 s LCD output RODC 40 k resistanceNote 2 common LCD output RODS 200 k resistanceNote 2 segment Notes 1 The boost...

Page 476: ...me Release by interrupt request Note s Note Selection of 212 fX 214 fX 215 fX 216 fX and 217 fX is possible using bits 0 to 2 OSTS0 to OSTS2 of the oscillation stabilization time select register OSTS...

Page 477: ...high voltageNote 9 7 10 0 10 3 V VDD supply current IDD 10 mA VPP supply current IPP VPP 10 V 75 100 mA Write time per byte TWRT 50 500 s Number of rewriting CWRT 20 times times Erase time TERASE 0 2...

Page 478: ...478 CHAPTER 25 ELECTRICAL SPECIFICATIONS User s Manual U15798EJ2V0UD Flash write mode setting timing tDRPSR tPSRON tPSRRF tRFCF tCL tCH tCOUNT VDD 0 V VPPH VPPL 0 V VDD 0 V VDD VPP RESET input...

Page 479: ...ows the characteristics curves of the time from the start of voltage boost VLCON 1 and the changes in the LCD output voltage when GAIN is set to 0 using the 3 V display panel LCD output voltage voltag...

Page 480: ...llowing shows the temperature characteristics curves of LCD output voltage LCD output voltage V 40 30 20 10 0 10 20 30 40 50 60 70 80 40 30 20 10 0 10 20 30 40 50 60 70 80 Temperature C LCD output vol...

Page 481: ...h lead centerline is located within 0 08 mm of its true position T P at maximum material condition ITEM MILLIMETERS A B D G 16 00 0 20 14 00 0 20 0 50 T P 1 00 J 16 00 0 20 K C 14 00 0 20 I 0 08 1 00...

Page 482: ...0 1 00 0 20 0 35 0 06 1 28 0 10 0 93 P113F1 80 DA3 0 50 0 05 0 10 UNIT mm x y y1 ZD ZE b INDEX MARK S w B D S w A E A B ZE ZD 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L y1 S e S x b A B M S y A A2...

Page 483: ...U 100 pin plastic LQFP fine pitch 14 14 PD780353YGC 8EU 100 pin plastic LQFP fine pitch 14 14 PD780354YGC 8EU 100 pin plastic LQFP fine pitch 14 14 PD78F0354GC 8EU 100 pin plastic LQFP fine pitch 14 1...

Page 484: ...frared reflow Package peak temperature 235 C Time 30 seconds max IR35 107 2 at 210 C or higher Count Two times or less Exposure limit 7 daysNote after that prebake at 125 C for 10 hours VPS Package pe...

Page 485: ...kage peak temperature 235 C Time 30 seconds max IR35 107 2 at 210 C or higher Count Two times or less Exposure limit 7 daysNote after that prebake at 125 C for 10 hours VPS Package peak temperature 21...

Page 486: ...shows the configuration example of the tools Support for PC98 NX series Unless otherwise specified products supported by IBM PC ATTM compatibles can be used for PC98 NX series computers When using PC9...

Page 487: ...compiler package Device file C library source fileNote 1 Debugging software Integrated debugger System simulator Host machine PC or EWS Interface adapter PC card interface etc In circuit emulator Emul...

Page 488: ...device file DF780354 sold separately Caution when using RA78K0 in PC environment This assembler package is a DOS based application It can also be used in Windows however by using the project manager i...

Page 489: ...s Rel 2 5 1 1 4 inch CGMT A 3 Control Software Project manager This is control software designed to enable efficient user program development in the Windows environment All operations used in developm...

Page 490: ...sed connected to the IE 78K0 NS With the addition of this board the addition of a coverage function enhancement of tracer and timer functions and other such debugging function enhancements are possibl...

Page 491: ...S SM78K0 ID78K0 NS This debugger supports the in circuit emulators for the 78K 0 Series The Integrated debugger ID78K0 NS is Windows based software supporting in circuit emulators It has improved C c...

Page 492: ...ompt when using in Windows Part number S RX78013 Caution When purchasing the RX78K0 fill in the purchase application form in advance and sign the user agreement Remark and in the part number differ de...

Page 493: ...094 n 2 7 0 106 ITEM MILLIMETERS INCHES B 0 5x24 12 0 020x0 945 0 472 C 0 5 0 020 A 21 55 0 848 D 0 5x24 12 0 020x0 945 0 472 H 10 9 0 429 I 13 3 0 524 J 15 7 0 618 E 15 0 0 591 F 21 55 G 3 55 0 140 0...

Page 494: ...a product of TOKYO ELETECH CORPORATION Table B 1 Distance Between IE System and Conversion Adapter When 100 Pin Plastic LQFP Is Used Emulation Probe Conversion Adapter Distance Between IE System and C...

Page 495: ...onditions of Target System When NP H100GC TQ Is Used Emulation probe NP 100GC 23 mm 25 mm 40 mm 34 mm Target system Connection adapter TGC 100SDW 21 55 mm Pin 1 11 mm Emulation board IE 780354 NS EM1...

Page 496: ...20 Correction control register CORCN 421 E 8 bit compare register A0 CRA0 160 8 bit compare register B0 CRB0 160 8 bit H width compare register B0 CRHB0 160 8 bit timer compare register 50 CR50 190 8...

Page 497: ...ct register OSTS 215 407 P Pin function switching register 8 PF8 110 Pin function switching register 9 PF9 110 Pin function switching register 10 PF10 110 Pin function switching register 11 PF11 110 P...

Page 498: ...CSIM3 267 16 bit timer capture compare register 00 CR00 129 16 bit timer capture compare register 01 CR01 130 16 bit timer counter 0 TM0 129 16 bit timer mode control register 0 TMC0 131 16 bit timer...

Page 499: ...90 CR51 8 bit timer compare register 51 190 CRA0 8 bit compare register A0 160 CRB0 8 bit compare register B0 160 CRC0 Capture compare control register 0 133 CRHB0 8 bit H width compare register B0 16...

Page 500: ...ter 10 110 PF11 Pin function switching register 11 110 PM0 Port mode register 0 106 165 221 PM2 Port mode register 2 106 PM3 Port mode register 3 106 136 194 PM4 Port mode register 4 106 PM7 Port mode...

Page 501: ...TM51 8 bit timer counter 51 190 TMA0 8 bit timer counter A0 161 TMB0 8 bit timer counter B0 161 TMC0 16 bit timer mode control register 0 131 TMC50 8 bit timer mode control register 50 192 TMC51 8 bi...

Page 502: ...ation of Figure 4 4 P10 to P17 Block Diagram FUNCTIONS Addition of Caution in 4 2 3 Port 2 Modification of Note in Format of Figure 4 18 Port Mode Registers PM0 PM2 to PM4 PM7 to PM11 Modification of...

Page 503: ...3 in Figure 13 2 Format of A D Converter 780354Y SUBSERIES Mode Register 0 ADM0 and addition of Table 13 2 Settings of ADCS0 and ADCE0 and Figure 13 3 Timing Chart When Boost Reference Voltage Genera...

Page 504: ...ion of Figure 17 22 Example of Slave to Master Communication When 9 Clock Wait Is Selected for Both Master and Slave Correction of Figure 18 1 LCD Controller Driver Block Diagram CHAPTER 18 LCD Modifi...

Page 505: ...Size Switching Register IMS CHAPTER 23 PD78F0354 78F0354Y Modification of Table 23 3 Communication Mode List Change of pin names and signal names in Figure 23 5 Example of Connection with Dedicated Fl...

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