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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0
User’s Manual U15798EJ2V0UD
CR00 is set by a 16-bit memory manipulation instruction.
RESET input makes the value of this register undefined.
Cautions 1. In the clear & start mode entered on a match between TM0 and CR00, set a value other than
0000H in CR00. However, in the free-running mode and in the clear mode using the valid
edge of TI00, if 0000H is set to CR00, an interrupt request (INTTM00) is generated following
overflow (FFFFH).
2. If the new value of CR00 is less than the value of 16-bit timer counter 0 (TM0), TM0 continues
counting, overflows, and then start counting from 0 again. If the new value of CR00 is less
than the old value, therefore, the timer must be reset and restarted after the value of CR00
is changed.
(3) 16-bit timer capture/compare register 01 (CR01)
CR01 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is
used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register 0 (CRC0).
•
When CR01 is used as a compare register
The value set in the CR01 is constantly compared with the 16-bit timer counter 0 (TM0) count value, and an
interrupt request (INTTM01) is generated if they match.
•
When CR01 is used as a capture register
It is possible to select the valid edge of the TI00/P35 pin as the capture trigger. The TI00/P35 valid edge is
set by means of prescaler mode register 0 (PRM0). Table 6-2 shows the setting when the valid edge of the
TI00/P35 pin is specified as the capture trigger.
CR01 is set by a 16-bit memory manipulation instruction.
RESET input makes the value of this register undefined.
Caution In the clear & start mode entered on a match between TM0 and CR00, set a value other than
0000H in CR01. However, in the free-running mode and in the clear mode using the valid edge
of TI00, if 0000H is set to CR01, an interrupt request (INTTM01) is generated following overflow
(FFFFH).
