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114
CHAPTER 5 CLOCK GENERATOR
User’s Manual U15798EJ2V0UD
Figure 5-1. Clock Generator Block Diagram
XT1
XT2
FRC
Subsystem
clock
oscillator
f
XT
4f
XT
Main system
clock
oscillator
f
X
Prescaler
f
X
2
f
X
2
2
f
X
2
3
f
X
2
4
f
XTT
2
1/2
SCT
×
4
multiplication
circuit
Prescaler
Timer 51,
watch timer,
clock output function
LCD controller/driver
Subclock select
register (SSCK)
Clock to peripheral
hardware
CPU clock
(f
CPU
)
Standby
controller
Wait
controller
3
Selector
STOP
MCC FRC
CLS
CSS PCC2 PCC1 PCC0
Processor clock control register
(PCC)
Internal bus
X1
X2
Selector
f
XTT
Remark
f
XTT
: f
XT
or 4f
XT