6
User’s Manual U15798EJ2V0UD
Major Revisions in This Edition (1/3)
Page
Description
Throughout
Deletion of indication “under development” for all target products
AV
REF
pin
→
AV
DD
pin
A/D converter operation enable voltage
AV
REF
= 2.7 to 5.5 V
→
AV
DD
= 2.2 to 5.5 V
p.33
Change of 113-pin plastic FBGA package in
1.4 Pin Configuration (Top View)
p.52
Modification of
Table 2-1 Pin I/O Circuit Types
p.61
Addition of description on program area in
3.1.2 (1) Internal high-speed RAM
and
(2) Internal
expansion RAM
pp.67, 68
Change of
Figure 3-10 Data To Be Saved to Stack Memory
and
Figure 3-11 Data To Be Restored
from Stack Memory
p.81
Modification of
[Description example]
in
3.4.4 Short direct addressing
pp.84 to 86
Addition of
[Illustration]
in
3.4.7 Based addressing, 3.4.8 Based indexed addressing
, and
3.4.9
Stack addressing
p.88
Modification of description of port 1 and port 4 in
Table 4-1 Port Functions
p.92
Modification of
Figure 4-4 P10 to P17 Block Diagram
p.93
Addition of
Caution
in
4.2.3 Port 2
p.107
Modification of
Note
in
Figure 4-18 Format of Port Mode Registers (PM0, PM2 to PM4, PM7 to
PM11)
p.110
Modification of setting and addition of
Caution 2
in
Figure 4-21 Format of Pin Function Switching
Registers (PF8 to PF11)
p.123
Addition of description in
5.5.1 Main system clock operations
p.128
Modification of
Figure 6-1 Block Diagram of 16-Bit Timer/Event Counter 0
p.140
Addition of
Figure 6-11 Configuration of PPG Output
and
Figure 6-12 PPG Output Operation
Timing
pp.152, 155
Modification of
6.6 (4) Capture register data retention timing
and addition of
(13) STOP mode and
main system clock stop mode settings
p.149 in 1st edition Deletion of <1> in
6.6 (7) Conflicting operations
in 1st edition
p.165
Modification of
Figure 7-6 Format of Carrier Generator Output Control Register B0
p.179
Addition of input frequency from TMIB0 pin in
Table 7-7 Square-Wave Output Range with 16-Bit
Resolution
p.190
Addition of description in
8.3 (2) 8-bit timer compare register 5n (CR5n: n = 0, 1)
p.198
Addition of
[Setting]
in
8.5.2 External event counter operation
p.199
Addition of description on frequencies in
[Setting]
in
8.5.3 Square-wave output operation
p.200
Modification of description of
[Setting]
in
8.5.4 PWM output operation
p.207
Correction of
Figure 9-2 Format of Watch Timer Operation Mode Register 0 (WTNM0)
p.224
Correction of
12.2 (3) Sample & hold circuit
and
(4) Voltage comparator
pp.227, 228
Modification of description of
Note 3
in
Figure 12-2 Format of A/D Converter Mode Register 0
(ADM0)
, and addition of
Table 12-2 Settings of ADCS0 and ADCE0
and
Figure 12-3 Timing Chart
When Boost Reference Voltage Generator Is Used
p.239
Modification of
Figure 12-12 Analog Input Pin Connection
Addition of the followings in
12.6 A/D Converter Cautions
p.239
(6)
Input impedance of ANI0 to ANI7 pins
p.242
(14) AV
DD
pin
