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CHAPTER 17 SERIAL INTERFACE IIC0 (
µ
PD780344Y, 780354Y SUBSERIES ONLY)
User’s Manual U15798EJ2V0UD
Figure 17-14. Wait Signal (2/2)
(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKE0 = 1)
SCL0
6
SDA0
7
8
9
1
2
3
SCL0
IIC0
6
H
7
8
1
2
3
D2
D1
D0
ACK
D7
D6
D5
9
IIC0
SCL0
ACKE0
Master
Master and slave both wait
after output of ninth clock
IIC0 data write (cancel wait)
Slave
FFH is written to IIC0 or WREL0 is set to 1
Output according to previously set ACKE0 value
Transfer lines
Wait signal
from master
and slave
Wait signal
from slave
Remark
ACKE0: Bit 2 of IIC control register 0 (IICC0)
WREL0: Bit 5 of IIC control register 0 (IICC0)
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0).
Normally, when bit 5 (WREL0) of IICC0 is set to 1 or when FFH is written to IIC shift register 0 (IIC0), the wait status
is canceled and the transmitting side writes data to IIC0 to cancel the wait status.
The master device can also cancel the wait status via either of the following methods.
• By setting bit 1 (STT0) of IICC0 to 1
• By setting bit 0 (SPT0) of IICC0 to 1
