503
APPENDIX D REVISION HISTORY
User’s Manual U15798EJ2V0UD
(2/4)
Edition
Major Revision from Previous Edition
Applied to:
2nd edition
Correction of
Figure 9-2 Format of Watch Timer Operation Mode Register
CHAPTER 9 WATCH TIMER
0 (WTNM0)
Correction of
12.2 (3) Sample & hold circuit
and
(4) Voltage comparator
CHAPTER 12 8-BIT A/D
Modification of description of
Note 3
in
Figure 12-2 Format of A/D Converter
CONVERTER (
µ
PD780344,
Mode Register 0 (ADM0)
, and addition of
Table 12-2 Settings of ADCS0
780344Y SUBSERIES)
and ADCE0
and
Figure 12-3 Timing Chart When Boost Reference Voltage
Generator Is Used
Modification of
Figure 12-12 Analog Input Pin Connection
Addition of the followings in
12.6 A/D Converter Cautions
(6)
Input impedance of ANI0 to ANI7 pins
(14) AV
DD
pin
Change of
Figure 12-16 Example of Connecting Capacitor to V
DD1
and
AV
REF
Pins
in 1st edition to
Figure 12-16 Example of Connecting Capacitor
to AV
DD
Pin
Modification of
Table 12-3 Resistances and Capacitances of Equivalent
Circuit (Reference Values)
Addition and modification of description in
13.2 (2) A/D conversion result
CHAPTER 13 10-BIT A/D
register 0 (ADCR0), (3) Sample & hold circuit
, and
(4) Voltage comparator
CONVERTER (
µ
PD780354,
Modification of description of
Note 3
in
Figure 13-2 Format of A/D Converter
780354Y SUBSERIES)
Mode Register 0 (ADM0)
, and addition of
Table 13-2 Settings of ADCS0
and ADCE0
and
Figure 13-3 Timing Chart When Boost Reference Voltage
Generator Is Used
Modification of
Figure 13-16 Analog Input Pin Connection
Addition of the followings in
13.6 A/D Converter Cautions
(6)
Input impedance of ANI0 to ANI7 pins
(14) AV
DD
pin
Change of
Figure 13-20 Example of Connecting Capacitor to V
DD1
and
AV
REF
Pins
in 1st edition to
Figure 13-20 Example of Connecting Capacitor
to AV
DD
Pin
Modification of
Table 13-3 Resistances and Capacitances of Equivalent
Circuit (Reference Values)
Modification of description of MODE flag in
Figure 14-2 Format of Serial
CHAPTER 14 SERIAL
Operation Mode Register 3 (CSIM3)
INTERFACE SIO3
Modification of
Caution 1
in
Figure 15-3 Format of Serial Clock Select
CHAPTER 15 SERIAL
Register 1 (CSIC1)
INTERFACE CSI1
Deletion of
15.4.2 (6) SCK1 pin
and
(7) SO1 pin
in 1st edition
Change of
Caution
in
Figure 16-3 Format of Asynchronous Serial Interface CHAPTER 16 SERIAL
Mode Register 0 (ASIM0)
INTERFACE UART0
Addition of baud rate calculation in
Remarks
in
Figure 16-5 Format of Baud
Rate Generator Control Register 0 (BRGC0)
Modification of description in
16.4.2 (2) (d) Reception
Change of
Caution
in
Figure 16-9 Timing of Asynchronous Serial Interface
Receive Completion Interrupt Request
Modification of
Caution 2
in
Figure 16-10 Receive Error Timing
