117
CHAPTER 5 CLOCK GENERATOR
User’s Manual U15798EJ2V0UD
The fastest instructions of
µ
PD780344, 780354, 780344Y, and 780354Y Subseries are carried out in two CPU
clocks. The relationship of the CPU clock (f
CPU
) and the minimum instruction execution time is shown in Table 5-2.
Table 5-2. Relationship of CPU Clock and Min. Instruction Execution Time
CPU Clock (f
CPU
)
Min. Instruction Execution Time: 2/(f
CPU
)
f
X
0.2
µ
s
f
X
/2
0.4
µ
s
f
X
/2
2
0.8
µ
s
f
X
/2
3
1.6
µ
s
f
X
/2
4
3.2
µ
s
f
XT
/2
122
µ
s
2f
XT
(when
×
4 circuit is used)
30.5
µ
s
f
X
= 10 MHz, f
XT
= 32.768 kHz
f
X
: Main system clock oscillation frequency
f
XT
: Subsystem clock oscillation frequency
(2) Subclock select register (SSCK)
This register is used to control the operation of the
×
4 subsystem clock multiplication circuit.
SSCK is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-4. Format of Subclock Select Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
SSCK
0
0
0
0
0
0
0
SCT
FF78H
Retained
Note
R/W
SCT
Control of
×
4 subsystem clock multiplication circuit
0
Operation stopped (subsystem clock source (32.768 kHz) supplied to the CPU)
1
Operation enabled (clock that is the subsystem clock multiplied by 4 (131 kHz) supplied to the CPU)
Note
The register is set to 00H only by RESET input.
Cautions 1. Always set bits 1 to 7 to 0.
2. Write to the SCT flag prior to setting the CSS flag to 1 following the release of reset. Write
operations following the first operation are invalid (input the RESET signal to rewrite).
3. The
×
4 circuit is stopped during the HALT period to lower the power consumption, even while
its operation is enabled by the SCT flag.
After the HALT mode has been released, the device waits for the duration of one source clock
of the subsystem clock and then starts operating on the
×
4 clock.
