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CHAPTER 17 SERIAL INTERFACE IIC0 (
µ
PD780344Y, 780354Y SUBSERIES ONLY)
User’s Manual U15798EJ2V0UD
(3) IIC transfer clock select register 0 (IICCL0)
This register is used to set the transfer clock for the I
2
C bus.
IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets IICCL0 to 00H.
Figure 17-5. Format of IIC Transfer Clock Select Register 0 (IICCL0) (1/2)
Address: FFA6H After reset: 00H R/W
Note 1
Symbol
7
6
5
4
3
2
1
0
IICCL0
0
0
CLD0
DAD0
SMC0
DFC0
0
CL00
CLD0
Detection of SCL0 line level (valid only when IICE0 = 1)
0
SCL0 line was detected at low level.
1
SCL0 line was detected at high level.
Condition for clearing (CLD0 = 0)
Condition for setting (CLD0 = 1)
• When the SCL0 line is at low level
• When the SCL0 line is at high level
• When IICE0 = 0
• When RESET is input
DAD0
Detection of SDA0 line level (valid only when IICE0 = 1)
0
SDA0 line was detected at low level.
1
SDA0 line was detected at high level.
Condition for clearing (DAD0 = 0)
Condition for setting (DAD0 = 1)
• When the SDA0 line is at low level
• When the SDA0 line is at high level
• When IICE0 = 0
• When RESET is input
SMC0
Operation mode switching
0
Operation in standard mode
1
Operation in high-speed mode
Condition for clearing (SMC0 = 0)
Condition for setting (SMC0 = 1)
• Cleared by instruction
• Set by instruction
• When RESET is input
DFC0
Control of digital filter operation
Note 2
0
Digital filter OFF
1
Digital filter ON
Notes 1.
Bits 4 and 5 are read-only bits.
2.
The digital filter can be used when in high-speed mode. The response time is slower when the digital
filter is used.
Remark
IICE0: Bit 7 of IIC control register 0 (IICC0)
