NEC mPD780344 Series, User Manual

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User’s Manual U15798EJ2V0UD
LIST OF FIGURES (4/8)
Figure No. Title Page
9-3 Format of Watch Timer Interrupt Time Select Register (WTIM) ........................................................... 208
9-4 Operation Timing of Watch Timer/Interval Timer .................................................................................. 209
10-1 Watchdog Timer Block Diagram ........................................................................................................... 210
10-2 Format of Watchdog Timer Clock Select Register (WDCS) ................................................................. 213
10-3 Format of Watchdog Timer Mode Register (WDTM) ............................................................................ 214
10-4 Format of Oscillation Stabilization Time Select Register (OSTS) ........................................................ 215
11-1 Block Diagram of Clock Output Controller ........................................................................................... 218
11-2 Format of Clock Output Select Register (CKS) .................................................................................... 220
11-3 Format of Port Mode Register 0 (PM0) ................................................................................................ 221
11-4 Remote Control Output Application Example ...................................................................................... 221
12-1 8-Bit A/D Converter Block Diagram ..................................................................................................... 223
12-2 Format of A/D Converter Mode Register 0 (ADM0) ............................................................................. 227
12-3 Timing Chart When Boost Reference Voltage Generator Is Used ....................................................... 228
12-4 Format of Analog Input Channel Specification Register 0 (ADS0) ...................................................... 229
12-5 Basic Operation of 8-Bit A/D Converter ............................................................................................... 231
12-6 Relationship Between Analog Input Voltage and A/D Conversion Result ............................................ 232
12-7 A/D Conversion by Hardware Start (When Falling Edge Is Specified) ................................................. 234
12-8 A/D Conversion by Software Start ....................................................................................................... 235
12-9 Overall Error ......................................................................................................................................... 236
12-10 Quantization Error ................................................................................................................................ 236
12-11 Example of Series Resistor String Circuit Configuration ..................................................................... 238
12-12 Analog Input Pin Connection ............................................................................................................... 239
12-13 A/D Conversion End Interrupt Request Generation Timing ................................................................. 240
12-14 Timing of Reading Conversion Result (When Conversion Result Is Undefined) ................................. 241
12-15 Timing of Reading Conversion Result (When Conversion Result Is Normal) ...................................... 241
12-16 Example of Connecting Capacitor to AV
DD
Pin .................................................................................... 242
12-17 Processing of AV
DD
Pin ........................................................................................................................ 242
12-18 Internal Equivalent Circuit of ANI0 to ANI7 Pins .................................................................................. 243
12-19 Example of Connection if Signal Source Impedance Is High ............................................................... 243
13-1 10-Bit A/D Converter Block Diagram ................................................................................................... 244
13-2 Format of A/D Converter Mode Register 0 (ADM0) ............................................................................. 247
13-3 Timing Chart When Boost Reference Voltage Generator Is Used ....................................................... 248
13-4 Format of Analog Input Channel Specification Register 0 (ADS0) ...................................................... 249
13-5 Basic Operation of 10-Bit A/D Converter ............................................................................................. 251
13-6 Relationship Between Analog Input Voltage and A/D Conversion Result ............................................ 252
13-7 A/D Conversion by Hardware Start (When Falling Edge Is Specified) ................................................. 254
13-8 A/D Conversion by Software Start ....................................................................................................... 255
13-9 Overall Error ......................................................................................................................................... 256
13-10 Quantization Error ................................................................................................................................ 256
13-11 Zero-Scale Error .................................................................................................................................. 257