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CHAPTER 10 WATCHDOG TIMER
User’s Manual U15798EJ2V0UD
(1) Watchdog timer clock select register (WDCS)
This register sets overflow time of the watchdog timer and the interval timer.
WDCS is set by an 8-bit memory manipulation instruction.
RESET input sets the value of this register to 00H.
Figure 10-2. Format of Watchdog Timer Clock Select Register (WDCS)
Address: FF42H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
WDCS
0
0
0
0
0
WDCS2
WDCS1
WDCS0
WDCS2
WDCS1
WDCS0
Overflow time of watchdog timer/interval timer
0
0
0
2
12
/f
X
(410
µ
s)
0
0
1
2
13
/f
X
(819
µ
s)
0
1
0
2
14
/f
X
(1.64 ms)
0
1
1
2
15
/f
X
(3.28 ms)
1
0
0
2
16
/f
X
(6.55 ms)
1
0
1
2
17
/f
X
(13.1 ms)
1
1
0
2
18
/f
X
(26.2 ms)
1
1
1
2
20
/f
X
(105 ms)
Remarks 1.
f
X
: Main system clock oscillation frequency
2.
Figures in parentheses are for operation with f
X
= 10 MHz
