CHAPTER 17 SERIAL INTERFACE IIC0 (
µ
PD780344Y, 780354Y SUBSERIES ONLY)
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User’s Manual U15798EJ2V0UD
Table 17-4. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration
Interrupt Request Generation Timing
During address transmission
At falling edge of eighth or ninth clock following byte transfer
Note 1
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK signal transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When stop condition is output (when SPIE0 = 1)
Note 2
When data is at low level while attempting to output a
At falling edge of eighth or ninth clock following byte transfer
Note 1
restart condition
When stop condition is detected while attempting to
When stop condition is output (when SPIE0 = 1)
Note 2
output a restart condition
When data is at low level while attempting to output a
At falling edge of eighth or ninth clock following byte transfer
Note 1
stop condition
When SCL0 is at low level while attempting to output a
restart condition
Notes 1.
When WTIM0 (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge
of the ninth clock. When WTIM0 = 0 and the extension code’s slave address is received, an interrupt
request occurs at the falling edge of the eighth clock.
2.
When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation.
Remark
SPIE0: Bit 4 of IIC control register 0 (IICC0)
17.5.13 Wakeup function
The I
2
C bus slave function is a function that generates an interrupt request (INTIIC0) when a local address and
extension code have been received.
This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when
addresses do not match.
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
output a start condition) to a slave device.
However, when a stop condition is detected, bit 4 (SPIE0) of IIC control register 0 (IICC0) is set regardless of the
wakeup function, and this determines whether interrupt requests are enabled or disabled.
