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PROGRAM CONTROL UNIT (PCU) ARCHITECTURE
5 - 6
PROGRAM CONTROL UNIT
MOTOROLA
interruptible since they are fetched only once. A single-instruction DO loop can be used
in place of a REP instruction if interrupts must be allowed.
5.3.3 Program Interrupt Controller
The PIC receives all interrupt requests, arbitrates among them, and generates the inter-
rupt vector address.
Interrupts have a flexible priority structure with levels that can range from zero to three.
Levels 0 (lowest level), 1, and 2 are maskable. Level 3 is the highest interrupt priority level
(IPL) and is not maskable. Two interrupt mask bits in the SR reflect the current IPL and
indicate the level needed for an interrupt source to interrupt the processor. Interrupts
cause the DSP to enter the exception processing state which is discussed fully in SEC-
TION 7 – PROCESSING STATES.
The four external interrupt sources include three external interrupt request inputs (IRQA,
IRQB, and NMI) and the RESET pin. IRQA and IRQB can be either level sensitive or neg-
ative edge triggered. The nonmaskable interrupt (NMI) is edge sensitive and is a level 3
interrupt. MODA/IRQA, MODB/IRQB, and MODC/NMI pins are sampled when RESET is
deasserted. The sampled values are stored in the operating mode register (OMR) bits
MA, MB, and MC, respectively (see Section 5.4.3 for information on the OMR). Only the
fourth external interrupt, RESET, and Illegal Instruction have higher priority than NMI.
The PIC also arbitrates between the different I/O peripherals. The currently selected pe-
ripheral supplies the correct vector address to the PIC.
5.3.4 Instruction Pipeline Format
The program control unit uses a three-level pipelined architecture in which concurrent in-
struction fetch, decode, and execution occur. This pipelined operation remains essentially
hidden from the user and makes programming straightforward. The pipeline is illustrated
in Figure 5-3, which shows the operations of each of the execution units and all initial con-
ditions necessary to follow the execution of the instruction sequence shown in the figure.
The pipeline is described in more detail in Section 7.2.1 Instruction Pipeline.
The first instruction, I1, should be interpreted as follows: multiply the contents of X0 by the
contents of Y0, add the product to the contents already in accumulator A, round the result
to the “nearest even,” store the result back in accumulator A, move the contents in X data
memory (pointed to by R0) into X0 and postincrement R0, and move the contents in Y
data memory (pointed to by R4) into Y1 and postincrement R4. The second instruction,
I2, should be interpreted as follows: clear accumulator A, move the contents in X0 into the
location in X data memory pointed to by R0 and postincrement R0. Before the clear oper-
Summary of Contents for DSP56K
Page 12: ...xii LIST of TABLES MOTOROLA List of Tables Continued Table Page Number Title Number ...
Page 13: ...MOTOROLA DSP56K FAMILY INTRODUCTION 1 1 SECTION 1 DSP56K FAMILY INTRODUCTION ...
Page 31: ...MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 1 SECTION 3 DATA ARITHMETIC LOGIC UNIT ...
Page 50: ...DATA ALU SUMMARY 3 20 DATA ARITHMETIC LOGIC UNIT MOTOROLA ...
Page 51: ...MOTOROLA ADDRESS GENERATION UNIT 4 1 SECTION 4 ADDRESS GENERATION UNIT ...
Page 77: ...MOTOROLA PROGRAM CONTROL UNIT 5 1 SECTION 5 PROGRAM CONTROL UNIT ...
Page 124: ...INSTRUCTION GROUPS 6 30 INSTRUCTION SET INTRODUCTION MOTOROLA ...
Page 125: ...MOTOROLA PROCESSING STATES 7 1 SECTION 7 PROCESSING STATES STOP WAIT EXCEPTION NORMAL RESET ...
Page 167: ...STOP PROCESSING STATE MOTOROLA PROCESSING STATES 7 43 ...
Page 168: ...STOP PROCESSING STATE 7 44 PROCESSING STATES MOTOROLA ...
Page 169: ...MOTOROLA PORT A 8 1 SECTION 8 PORT A ...
Page 176: ...PORT A INTERFACE 8 8 PORT A MOTOROLA ...
Page 177: ...MOTOROLA PLL CLOCK OSCILLATOR 9 1 SECTION 9 PLL CLOCK OSCILLATOR x x d Φ VCO ...
Page 191: ...10 2 ON CHIP EMULATION OnCE MOTOROLA SECTION 10 ON CHIP EMULATION OnCE ...
Page 218: ...USING THE OnCE MOTOROLA ON CHIP EMULATION OnCE 10 29 ...
Page 604: ...INSTRUCTION ENCODING A 338 INSTRUCTION SET DETAILS MOTOROLA ...
Page 605: ...MOTOROLA BENCHMARK PROGRAMS B 1 APPENDIX B BENCHMARK PROGRAMS T T T T T P1 P3 P2 P4 T T T ...
Page 609: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 5 ...
Page 611: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 7 ...
Page 613: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 9 ...
Page 615: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 11 ...