NORMAL PROCESSING STATE
MOTOROLA
PROCESSING STATES
7 - 5
Case 2:
One of the more common sequences where pipeline effects are apparent is as
follows:
•
;Move a number into register Rn (n=0–7).
•
MOVE #xx,Rn
MOVE X:(Rn),A
;Use the new contents of Rn to address memory.
•
•
In this case, before the first MOVE instruction has written Rn during its execution cycle,
the second MOVE has accessed the old Rn, using the old contents of Rn. This is
because the address for indirect moves is formed during the decode cycle. This overlap-
ping instruction execution in the pipeline causes the pipeline effect. One instruction cycle
should be allowed after an address register has been written by a MOVE instruction
before the new contents are available for use as an address register by another MOVE
instruction. The proper instruction sequence is as follows:
•
;Move a number into register Rn.
•
MOVE X0,Rn
NOP
;Execute any instruction or instruction
•
;sequence not using Rn.
•
MOVE X:(Rn),A
Use the new contents of Rn.
Case 3:
A situation related to Case 2 can be seen in the boot ROM code shown in AP-
PENDIX A of the
DSP56001 Technical Data Sheet
. At the end of the bootstrap operation,
the operation mode register (OMR) is changed to mode #2, and then the program that was
loaded is executed. This process is accomplished in the last three instructions:
_BOOTEND
MOVEC
#2,OMR
;Set the operating mode to 2
;(and trigger an exit from
;bootstrap mode).
ANDI
#$0,CCR
;Clear SR as if RESET and
;introduce delay needed for
;Op. Mode change.
JMP
<$0
;Start fetching from PRAM, P:$0000
The JMP instruction generates its jump address during its decode cycle. If the JMP
instruction followed the MOVEC, the MOVEC instruction would not have changed the
OMR before the JMP instruction formed the fetch address. As a result, the jump would
fetch the instruction at P:$0000 of the bootstrap ROM (MOVE #$FFE9,R2). The OMR
would then change due to the MOVEC instruction, and the next instruction would be the
Summary of Contents for DSP56K
Page 12: ...xii LIST of TABLES MOTOROLA List of Tables Continued Table Page Number Title Number ...
Page 13: ...MOTOROLA DSP56K FAMILY INTRODUCTION 1 1 SECTION 1 DSP56K FAMILY INTRODUCTION ...
Page 31: ...MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 1 SECTION 3 DATA ARITHMETIC LOGIC UNIT ...
Page 50: ...DATA ALU SUMMARY 3 20 DATA ARITHMETIC LOGIC UNIT MOTOROLA ...
Page 51: ...MOTOROLA ADDRESS GENERATION UNIT 4 1 SECTION 4 ADDRESS GENERATION UNIT ...
Page 77: ...MOTOROLA PROGRAM CONTROL UNIT 5 1 SECTION 5 PROGRAM CONTROL UNIT ...
Page 124: ...INSTRUCTION GROUPS 6 30 INSTRUCTION SET INTRODUCTION MOTOROLA ...
Page 125: ...MOTOROLA PROCESSING STATES 7 1 SECTION 7 PROCESSING STATES STOP WAIT EXCEPTION NORMAL RESET ...
Page 167: ...STOP PROCESSING STATE MOTOROLA PROCESSING STATES 7 43 ...
Page 168: ...STOP PROCESSING STATE 7 44 PROCESSING STATES MOTOROLA ...
Page 169: ...MOTOROLA PORT A 8 1 SECTION 8 PORT A ...
Page 176: ...PORT A INTERFACE 8 8 PORT A MOTOROLA ...
Page 177: ...MOTOROLA PLL CLOCK OSCILLATOR 9 1 SECTION 9 PLL CLOCK OSCILLATOR x x d Φ VCO ...
Page 191: ...10 2 ON CHIP EMULATION OnCE MOTOROLA SECTION 10 ON CHIP EMULATION OnCE ...
Page 218: ...USING THE OnCE MOTOROLA ON CHIP EMULATION OnCE 10 29 ...
Page 604: ...INSTRUCTION ENCODING A 338 INSTRUCTION SET DETAILS MOTOROLA ...
Page 605: ...MOTOROLA BENCHMARK PROGRAMS B 1 APPENDIX B BENCHMARK PROGRAMS T T T T T P1 P3 P2 P4 T T T ...
Page 609: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 5 ...
Page 611: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 7 ...
Page 613: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 9 ...
Page 615: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 11 ...