EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
7 - 18
PROCESSING STATES
MOTOROLA
CAUTION
On all level-sensitive interrupts, the interrupt must be externally released be-
fore interrupts are internally re-enabled. Otherwise, the processor will be in-
terrupted repeatedly until the release of the level-sensitive interrupt occurs.
The edge sensitive NMI is a priority 3 interrupt and cannot be masked. Only RESET and
illegal instruction have higher priority than NMI.
7.3.3.2 Software Interrupt Sources
There are two software interrupt sources — software interrupt (SWI) and illegal instruc-
tion interrupt (III).
SWI is a nonmaskable interrupt (IPL 3), which is serviced immediately following the SWI
instruction execution, usually using a long interrupt service routine. The difference
between an SWI and a JSR instruction is that the SWI sets the interrupt mask to prevent
interrupts below IPL 3 from being serviced. The SWI’s ability to mask out lower level
interrupts makes it very useful for setting breakpoints in monitor programs. The JSR
instruction does not affect the interrupt mask.
The III is also a nonmaskable interrupt (IPL 3). It is serviced immediately following the
execution or the attempted execution of an illegal instruction (any undefined operation
code). IIIs are fatal errors. Only a long interrupt routine should be used for the III routine.
RTI or RTS should not be used at the end of the interrupt routine because, during the III
service, the JSR located in the III vector will normally stack the address of the illegal
instruction (see Figure 7-4). Returning from the interrupt routine would cause the proces-
sor to attempt to execute the illegal interrupt again and cause an infinite loop which can
only be broken by cycling power. This long interrupt (see Figure 7-4) can be used as a
diagnostic tool to allow the programmer to examine the stack (MOVE SSH, dest) and
locate the illegal instruction, or the application program can be restarted with the hope
that the failure was a soft error. The illegal instruction is useful for triggering the illegal
interrupt service routine to see if the III routine can recover from illegal instructions.
Summary of Contents for DSP56K
Page 12: ...xii LIST of TABLES MOTOROLA List of Tables Continued Table Page Number Title Number ...
Page 13: ...MOTOROLA DSP56K FAMILY INTRODUCTION 1 1 SECTION 1 DSP56K FAMILY INTRODUCTION ...
Page 31: ...MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 1 SECTION 3 DATA ARITHMETIC LOGIC UNIT ...
Page 50: ...DATA ALU SUMMARY 3 20 DATA ARITHMETIC LOGIC UNIT MOTOROLA ...
Page 51: ...MOTOROLA ADDRESS GENERATION UNIT 4 1 SECTION 4 ADDRESS GENERATION UNIT ...
Page 77: ...MOTOROLA PROGRAM CONTROL UNIT 5 1 SECTION 5 PROGRAM CONTROL UNIT ...
Page 124: ...INSTRUCTION GROUPS 6 30 INSTRUCTION SET INTRODUCTION MOTOROLA ...
Page 125: ...MOTOROLA PROCESSING STATES 7 1 SECTION 7 PROCESSING STATES STOP WAIT EXCEPTION NORMAL RESET ...
Page 167: ...STOP PROCESSING STATE MOTOROLA PROCESSING STATES 7 43 ...
Page 168: ...STOP PROCESSING STATE 7 44 PROCESSING STATES MOTOROLA ...
Page 169: ...MOTOROLA PORT A 8 1 SECTION 8 PORT A ...
Page 176: ...PORT A INTERFACE 8 8 PORT A MOTOROLA ...
Page 177: ...MOTOROLA PLL CLOCK OSCILLATOR 9 1 SECTION 9 PLL CLOCK OSCILLATOR x x d Φ VCO ...
Page 191: ...10 2 ON CHIP EMULATION OnCE MOTOROLA SECTION 10 ON CHIP EMULATION OnCE ...
Page 218: ...USING THE OnCE MOTOROLA ON CHIP EMULATION OnCE 10 29 ...
Page 604: ...INSTRUCTION ENCODING A 338 INSTRUCTION SET DETAILS MOTOROLA ...
Page 605: ...MOTOROLA BENCHMARK PROGRAMS B 1 APPENDIX B BENCHMARK PROGRAMS T T T T T P1 P3 P2 P4 T T T ...
Page 609: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 5 ...
Page 611: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 7 ...
Page 613: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 9 ...
Page 615: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 11 ...