OnCE TRACE LOGIC
10- 14
ON-CHIP EMULATION (OnCE)
MOTOROLA
points, OMLLR must be loaded by the external command controller.
10.4.4
Memory High Address Comparator (OMHC)
The OMHC compares the current memory address (stored in OMAL) with the OMULR
contents. If OMULR is higher than or equal to OMAL then the comparator delivers a signal
indicating that the address is lower than or equal to the upper limit.
10.4.5
Memory Low Address Comparator (OMLC)
The OMLC compares the current memory address (stored in OMAL) with the OMLLR con-
tents. If OMLLR is lower than or equal to OMAL then the comparator delivers a signal in-
dicating that the address is higher than or equal to the lower limit.
10.4.6
Memory Breakpoint Counter (OMBC)
The 24-bit OMBC is loaded with a value equal to the number of times, minus one, that a
memory access event should occur before a memory breakpoint is declared. The memory
access event is specified by the BC3-BC0 bits in the OSCR register and by the memory
upper and lower limit registers. On each occurrence of the memory access event, the
breakpoint counter is decremented. When the counter has reached the value of zero and
a new occurrence takes place, the chip will enter the debug mode. The OMBC can be
read, written, or cleared through the OnCE serial interface.
Anytime the upper or lower limit registers are changed, or a different breakpoint event is
selected in the OSCR, the breakpoint counter must be written afterward. This assures that
the OnCE breakpoint logic is reset and that no previous events will affect the new break-
point event selected.
The breakpoint counter is cleared by hardware reset.
10.5
OnCE TRACE LOGIC
The OnCE trace logic allows the user to execute instructions in single or multiple steps
before the chip returns to the debug mode and awaits OnCE commands from the debug
serial port. (The OnCE trace logic is independent of the trace facility of the
DSP56000/56001, which is operated through the trace interrupt discussed in Section
7.3.3.3, and started by setting the trace bit in the processor’s status register discussed in
Section 5.4.2.12). The OnCE trace logic block diagram is shown in Figure 10-7.
Summary of Contents for DSP56K
Page 12: ...xii LIST of TABLES MOTOROLA List of Tables Continued Table Page Number Title Number ...
Page 13: ...MOTOROLA DSP56K FAMILY INTRODUCTION 1 1 SECTION 1 DSP56K FAMILY INTRODUCTION ...
Page 31: ...MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 1 SECTION 3 DATA ARITHMETIC LOGIC UNIT ...
Page 50: ...DATA ALU SUMMARY 3 20 DATA ARITHMETIC LOGIC UNIT MOTOROLA ...
Page 51: ...MOTOROLA ADDRESS GENERATION UNIT 4 1 SECTION 4 ADDRESS GENERATION UNIT ...
Page 77: ...MOTOROLA PROGRAM CONTROL UNIT 5 1 SECTION 5 PROGRAM CONTROL UNIT ...
Page 124: ...INSTRUCTION GROUPS 6 30 INSTRUCTION SET INTRODUCTION MOTOROLA ...
Page 125: ...MOTOROLA PROCESSING STATES 7 1 SECTION 7 PROCESSING STATES STOP WAIT EXCEPTION NORMAL RESET ...
Page 167: ...STOP PROCESSING STATE MOTOROLA PROCESSING STATES 7 43 ...
Page 168: ...STOP PROCESSING STATE 7 44 PROCESSING STATES MOTOROLA ...
Page 169: ...MOTOROLA PORT A 8 1 SECTION 8 PORT A ...
Page 176: ...PORT A INTERFACE 8 8 PORT A MOTOROLA ...
Page 177: ...MOTOROLA PLL CLOCK OSCILLATOR 9 1 SECTION 9 PLL CLOCK OSCILLATOR x x d Φ VCO ...
Page 191: ...10 2 ON CHIP EMULATION OnCE MOTOROLA SECTION 10 ON CHIP EMULATION OnCE ...
Page 218: ...USING THE OnCE MOTOROLA ON CHIP EMULATION OnCE 10 29 ...
Page 604: ...INSTRUCTION ENCODING A 338 INSTRUCTION SET DETAILS MOTOROLA ...
Page 605: ...MOTOROLA BENCHMARK PROGRAMS B 1 APPENDIX B BENCHMARK PROGRAMS T T T T T P1 P3 P2 P4 T T T ...
Page 609: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 5 ...
Page 611: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 7 ...
Page 613: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 9 ...
Page 615: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 11 ...