![background image](http://html.mh-extra.com/html/motorola/dsp56k/dsp56k_manual_246569561.webp)
INSTRUCTION TIMING
MOTOROLA
INSTRUCTION SET DETAILS
A - 295
including the number of words per instruction, the addressing mode, whether the instruc-
tion fetch pipe is full or not, the number of external bus accesses, and the number of wait
states inserted in each external access. The symbols used reference subsequent tables
to complete the execution clock cycle count.
All tables are based on the following assumptions:
1. All instruction cycles are counted in
oscillator clock cycles
.
2. The instruction fetch pipeline is
full
.
3. There is no contention for
instruction
fetches. Thus, external program instruc-
tion fetches are assumed not to have to contend with external data memory
accesses.
4. There are no wait states for
instruction
fetches done sequentially (as for non-
change-of-flow instructions), but they are taken into account for change-of-flow
instructions which flush the pipeline such as JMP, Jcc, RTI, etc.
To help the user better understand and use the timing tables, the following three exam-
ples illustrate the tables’ “layered’’ nature. (Remember that it is faster and simpler to use
the DSP56K simulator to calculate instruction timing.)
Example 16: Arithmetic Instruction with Two Parallel Moves
Problem:
Calculate the number of 24-bit instruction program words and the number of
oscillator clock cycles required for the instruction
MACR –X0,X0,A
X1,X:(R6)–
Y0,Y:(R0)+
where
Operating Mode Register (OMR)
= $02 (normal expanded memory map),
Bus Control Register (BCR)
= $1135,
R6 Address Register
= $0052 (internal X memory), and
R0 Address Register
= $0523 (external Y memory).
Solution:
To determine the number of instruction program words and the number of
oscillator clock cycles required for the given instruction, the user should perform the fol-
lowing operations:
1. Look up the number of instruction program words and the number of oscillator clock
cycles required for the opcode-operand portion of the instruction in Table A-6.
According to Table A-6, the MACR instruction will require (1+mv) instruction program
words and will execute in (2+mv) oscillator clock cycles. The term “mv’’ represents the
additional (if any) instruction program words and the additional (if any) oscillator clock
Summary of Contents for DSP56K
Page 12: ...xii LIST of TABLES MOTOROLA List of Tables Continued Table Page Number Title Number ...
Page 13: ...MOTOROLA DSP56K FAMILY INTRODUCTION 1 1 SECTION 1 DSP56K FAMILY INTRODUCTION ...
Page 31: ...MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 1 SECTION 3 DATA ARITHMETIC LOGIC UNIT ...
Page 50: ...DATA ALU SUMMARY 3 20 DATA ARITHMETIC LOGIC UNIT MOTOROLA ...
Page 51: ...MOTOROLA ADDRESS GENERATION UNIT 4 1 SECTION 4 ADDRESS GENERATION UNIT ...
Page 77: ...MOTOROLA PROGRAM CONTROL UNIT 5 1 SECTION 5 PROGRAM CONTROL UNIT ...
Page 124: ...INSTRUCTION GROUPS 6 30 INSTRUCTION SET INTRODUCTION MOTOROLA ...
Page 125: ...MOTOROLA PROCESSING STATES 7 1 SECTION 7 PROCESSING STATES STOP WAIT EXCEPTION NORMAL RESET ...
Page 167: ...STOP PROCESSING STATE MOTOROLA PROCESSING STATES 7 43 ...
Page 168: ...STOP PROCESSING STATE 7 44 PROCESSING STATES MOTOROLA ...
Page 169: ...MOTOROLA PORT A 8 1 SECTION 8 PORT A ...
Page 176: ...PORT A INTERFACE 8 8 PORT A MOTOROLA ...
Page 177: ...MOTOROLA PLL CLOCK OSCILLATOR 9 1 SECTION 9 PLL CLOCK OSCILLATOR x x d Φ VCO ...
Page 191: ...10 2 ON CHIP EMULATION OnCE MOTOROLA SECTION 10 ON CHIP EMULATION OnCE ...
Page 218: ...USING THE OnCE MOTOROLA ON CHIP EMULATION OnCE 10 29 ...
Page 604: ...INSTRUCTION ENCODING A 338 INSTRUCTION SET DETAILS MOTOROLA ...
Page 605: ...MOTOROLA BENCHMARK PROGRAMS B 1 APPENDIX B BENCHMARK PROGRAMS T T T T T P1 P3 P2 P4 T T T ...
Page 609: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 5 ...
Page 611: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 7 ...
Page 613: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 9 ...
Page 615: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 11 ...