NORMAL PROCESSING STATE
7 - 4
PROCESSING STATES
MOTOROLA
Each instruction requires a minimum of three instruction cycles (12 clock phases) to be
fetched, decoded, and executed. This means that there is a delay of three instruction
cycles on powerup to fill the pipe. A new instruction may begin immediately following the
previous instruction. Two-word instructions require a minimum of four instruction cycles
to execute (three cycles for the first instruction word to move through the pipe and exe-
cute and one more cycle for the second word to execute). A new instruction may start
after two instruction cycles.
The pipeline is normally transparent to the user. However, there are certain instruction-
sequence dependent situations where the pipeline will affect the program execution.
Such situations are best described by case studies. Most of these restricted sequences
occur because 1) all addresses are formed during instruction decode, or 2) they are the
result of contention for an internal resource such as the status register (SR). If the execu-
tion of an instruction depends on the relative location of the instruction in a sequence of
instructions, there is a pipeline effect. To test for a suspected pipeline effect, compare
between the execution of the suspect instruction 1) when it directly follows the previous
instruction and 2) when four NOPs are inserted between the two. If there is a difference,
it is caused by a pipeline effect. The DSP56K assembler flags instruction sequences with
potential pipeline effects so that the user can determine if the operation will execute as
expected.
Case 1:
The following two examples show similar code sequences.
1. No pipeline effect:
ORI #xx,CCR
;Changes CCR at the end of execution time slot
Jcc xxxx
;Reads condition codes in SR in its execution time slot
The Jcc will test the bits modified by the ORI without any pipeline effect in the code seg-
ment above.
2. Instruction that started execution during decode:
ORI #04,OMR
;Sets DE bit at execution time slot
MOVE x:$100,a
;Reads external RAM instead of internal ROM
A pipeline effect occurs in example 2 because the address of the MOVE is formed at its
decode time before the ORI changes the DE bit (which changes the memory map) in the
ORI’s execution time slot. The following code produces the expected results of reading
the internal ROM:
ORI #04,OMR
;Sets DE bit at execution time slot
NOP
;Delays the MOVE so it will read the updated memory map
MOVE x:$100,a
;Reads internal ROM
Summary of Contents for DSP56K
Page 12: ...xii LIST of TABLES MOTOROLA List of Tables Continued Table Page Number Title Number ...
Page 13: ...MOTOROLA DSP56K FAMILY INTRODUCTION 1 1 SECTION 1 DSP56K FAMILY INTRODUCTION ...
Page 31: ...MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 1 SECTION 3 DATA ARITHMETIC LOGIC UNIT ...
Page 50: ...DATA ALU SUMMARY 3 20 DATA ARITHMETIC LOGIC UNIT MOTOROLA ...
Page 51: ...MOTOROLA ADDRESS GENERATION UNIT 4 1 SECTION 4 ADDRESS GENERATION UNIT ...
Page 77: ...MOTOROLA PROGRAM CONTROL UNIT 5 1 SECTION 5 PROGRAM CONTROL UNIT ...
Page 124: ...INSTRUCTION GROUPS 6 30 INSTRUCTION SET INTRODUCTION MOTOROLA ...
Page 125: ...MOTOROLA PROCESSING STATES 7 1 SECTION 7 PROCESSING STATES STOP WAIT EXCEPTION NORMAL RESET ...
Page 167: ...STOP PROCESSING STATE MOTOROLA PROCESSING STATES 7 43 ...
Page 168: ...STOP PROCESSING STATE 7 44 PROCESSING STATES MOTOROLA ...
Page 169: ...MOTOROLA PORT A 8 1 SECTION 8 PORT A ...
Page 176: ...PORT A INTERFACE 8 8 PORT A MOTOROLA ...
Page 177: ...MOTOROLA PLL CLOCK OSCILLATOR 9 1 SECTION 9 PLL CLOCK OSCILLATOR x x d Φ VCO ...
Page 191: ...10 2 ON CHIP EMULATION OnCE MOTOROLA SECTION 10 ON CHIP EMULATION OnCE ...
Page 218: ...USING THE OnCE MOTOROLA ON CHIP EMULATION OnCE 10 29 ...
Page 604: ...INSTRUCTION ENCODING A 338 INSTRUCTION SET DETAILS MOTOROLA ...
Page 605: ...MOTOROLA BENCHMARK PROGRAMS B 1 APPENDIX B BENCHMARK PROGRAMS T T T T T P1 P3 P2 P4 T T T ...
Page 609: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 5 ...
Page 611: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 7 ...
Page 613: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 9 ...
Page 615: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 11 ...