Microwave networks CM7, User Manual

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Section 3-9 DEMOD
Page 3-9-2 CM 100Base-T System User’s Manual
Functional Description
The DEMOD (demodulator), Figure 3-9-2, accepts a QAM signal centered at 70 MHz
from the RXU and removes the modulation to produce I and Q baseband signals. A/D
converters sample the I and Q signals and send the output to the adaptive time domain
equalizer (ATDE). An FPGA configures and controls the ATDE and is also responsible
for the data demapping and decision-directed loops of the ATDE output. The ATDE
provides higher order signal compensation.
The FPGA extracts symbol clock timing from the equalized I and Q signals. A
differential signal from the FPGA drives a VCXO. The demapped I and Q data streams
go to the MUX for conversion back to error-corrected data and overhead.
Analog control loops provide I and Q coarse AGC and slope equalization. A slope
equalizer circuit detects the slope of the baseband signals to assist the coarse AGC
control voltage. Amplitude slope equalization provides first-order multipath
compensation.
Figure 3-9-2. DEMOD Block Diagram