37
x444/x444
Read DRAM (EDO/FPM) timings are 4-4-4/4-4-4
x222/x333 timings is the default.
This sets the timing for burst mode writes from
DRAM. Burst rea d a nd write requests a re genera ted by the CPU in four sepa ra te
pa rts. The first pa rt provides the loca tion within the DRAM where the rea d or
write is to ta ke pla ce while the rema ining three pa rts provide the a ctua l da ta. The
lower the timing numbers, the fa ster the system will a ddress memory.
x222
Write DRAM timings are 2-2-2-2
x333
Write DRAM timings are 3-3-3-3
x444
Write DRAM timings are 4-4-4-4
x222 timings is the default.
The turbo read leadoff may be required in certain system designs to support
layouts or faster memories.
Disabled is the default.
The 430HX chipset is ca pa ble of a llowing a DRAM rea d request to be genera ted
slightly before the a ddress ha s been fully decoded. This ca n reduce a ll rea d
la tencies.
More simply, the CPU will issue a rea d request a nd included with this request is
the pla ce (a ddress) in memory where the desired da ta is to be found. This request
is received by the DRAM controller. When the peculative Leadoff’ is enabled,
the controller will issue the rea d comma nd slightly before it ha s finished
determining the a ddress.
DRAM Write Burst
Timing
Turbo Read
Leadoff
DRAM Speculative
Leadoff