36
DRAM must continua lly be refreshed or it will lose its da ta . Norma lly, DRAM is
refreshed entirely a s the result of a single request. This option a llows you to
determine the number of CPU clocks a lloca ted for the
R
ow
A
ddress
S
trobe to
a ccumula te its cha rge before the DRAM is refreshed. If insufficient time is
a llowed, refresh ma y be incomplete a nd da ta lost.
3
Three clocks.
4
Four clocks.
Four clocks is the default.
This sets the number of CPU clocks a llowed before rea ds a nd writes to DRAM
a re performed.
7/6
Seven clocks leadoff for reads and six clocks leadoff for writes.
6/5
Six clocks leadoff for reads and five clocks leadoff for writes.
7/6 Leadoff timing is the default.
When DRAM is refreshed, both rows a nd columns a re a ddressed sepa ra tely. This
setup item a llows you to determine the timing of the tra nsition from Row Address
Strobe (RAS) to Column Address Strobe (CAS).
3
Three CPU clock delay.
2
Two CPU clock delay.
3 CPU clocks is the default.
This sets the timing for burst mode rea ds from two different DRAM(EDO/FPM).
Burst rea d a nd write requests a re genera ted by the CPU in four sepa ra te pa rts.
The first pa rt provides the loca tion within the DRAM where the rea d or write is to
ta ke pla ce while the rema ining three pa rts provide the a ctua l da ta. The lower the
timing numbers, the fa ster the system will a ddress memory.
x222/x333
Read DRAM (EDO/FPM) timings are 2-2-2/3-3-3
x333/x444
Read DRAM (EDO/FPM) timings are 3-3-3/4-4-4
DRAM R/W Leadoff
Timing
Fast RAS# to
CAS# Delay
DRAM Read
<EDO/FPM>