Intel 810A3, Design Manual

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Clocking
6-6 Intel
®
810A3 Chipset Design Guide
6.4 Capacitor Sites
Intel recommends 0603 package capacitor sites placed as close as possible to the clock input
receivers for AC tuning for the following signal groups:
•
GMCH
•
Processor
•
SDRAM/DCLK
•
3V66
•
3V66 to the ICH0/ICH
6.5 Clock Power Decoupling Guidelines
Several general layout guidelines should be followed when laying out the power planes for the
CK810 clock generator.
•
Isolate power planes to the each of the clock groups.
•
Place local decoupling as close to power pins as possible and connect with short, wide traces
and copper.
•
Connect pins to appropriate power plane with power vias (larger than signal vias).
•
Bulk decoupling should be connected to plane with 2 or more power vias.
•
Minimize clock signal routing over plane splits.
•
Do not route any signals underneath the clock generator on the component side of the board.
•
An example signal via is a 14 mil finished hole with a 24–26 mil path. An example power via
is an 18 mil finished hole with a 33–38 mil path. For large decoupling or power planes with
large current transients it is recommended to use a larger power via.
Figure 6-3. Example of Capacitor Placement Near Clock Input Receiver
CPU BCLK CPU BCLK
GMCH HTCLK GMCH HTCLK
GMCH SCLK
GMCH SCLK