Intel 810A3, Design Manual

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Intel
®
810A3 Chipset Design Guide 7-5
System Design Considerations
2.5V
The 2.5V plane powers the 2.5V rail of the clock synthesizer and the CMOS pullups to the
processor. This voltage is obtained from using a 2.5V voltage regulator that regulates the voltage
from the 3.3V power supply voltage (or the 5V power supply voltage).
Note: This regulator is required in ALL designs.
3.3VSB
The 3.3VSB plane powers the suspend well of the ICH, the ICH Real Time Clock, the AC’97
AMR connector, the 2 DIMM slots, and the PCI 3.3Vaux suspend power pins.
The 3.3Vaux requirement state that during suspend, the system must deliver 375 mA to each wake-
enabled card and 20 mA to each non wake-enabled card. During full-power operation, the system
must be able to supply 375 mA to EACH card. Therefore, the total current requirement for the PCI
3.3Vaux suspend power pins is:
•
Full-power Operation: 375 mA*number of PCI slots
•
Suspend Operation: 375+20*(number of PCI slots – 1)
The total maximum current requirement for the 3.3VSB power plane (as well as the 3.3V
regulator) is 7.12 A.
Note: This regulator is required in ALL designs.
7.1.2 LED Indicator for S0-S5 States
Although not required by the ACPI Specification, Intel recommends that an on-board LED be
implemented that informs the user that the system is in a full-on or a sleep state (as opposed to a
mechanical off state). In general, depending on the particular implementation, it may not be safe to
add/remove hardware to the system while the system is in an S5 state. Since the S5 state may
closely resemble the mechanical off state, (i.e., display blank, fans off, no noise, etc.) this LED
indicator, when lit, lets the user know that it is NOT safe to add/remove hardware to the system.
Implementation of this LED indicator may help prevent hardware damage to the system when a
user is changing hardware. This may be implemented by connecting an LED to one of the auxiliary
power supplies.