Intel 810A3, Design Manual, Page: 60 / 166

Layout and Routing Guidelines
4-8 Intel
®
810A3 Chipset Design Guide
4.6.1 Display Cache Solution Space
NOTE: Trace Length (inches)
Table 4-2. Display Cache Routing (Topology 1)
Trace (mils) A (inches)
Signal Topology Width Spacing Min Max
LMD[31:0], LDQM[3:0] 1 5 7 1 5
Figure 4-9. Display Cache (Topology 2)
Table 4-3. Display Cache Routing (Topology 2)
Trace (units=mils) B (inches) C (inches)
Signal Topology Width Spacing Min Max Min Max
LMA[11:0], LWE#, LCS#, LRAS#, LCAS# 2 5 7 1 3.75 0.75 1.25
Figure 4-10. Display Cache (Topology 3)
Table 4-4. Display Cache Routing (Topology 3)
Trace (units=mils) D (inches) E (inches) F (inches)
Signal Topology Width Spacing Length Min Max Min Max
TCLK 3 5 7 0.5 1.5 2.5 0.75 1.25
1 M x 1 6
1 M x 1 6
B
C
C
1 M x 1 6
1 M x 1 6
D E
F
F
2 2 O h m s