Layout and Routing Guidelines
4-12
Intel
®
810A3 Chipset Design Guide
4.8
Ultra ATA/66
4.8.1
IDE Routing Guidelines
This section contains guidelines for connecting and routing the ICH IDE interface. The ICH has
two independent IDE channels. This section provides guidelines for IDE connector cabling and
motherboard design, including component and resistor placement, and signal termination for both
IDE channels. The ICH0 and the ICH has integrated the series terminating resistors that have been
typically required on the IDE data and control signals running to the two ATA connectors.
The IDE interface can be routed with 5 mil traces on 5 mil spaces and should be less than 8 inches
long (from ICH to IDE connector). Additionally, the shortest IDE signal (on a given IDE channel)
must be less than 1” shorter than the longest IDE signal (on the channel).
Cabling
•
Length of Cable: Each IDE cable should be equal to or less than 18 inches.
•
Capacitance: Less than 30 pF.
•
Placement: A maximum of 6 inches between drive connectors on the cable. If a single drive is
placed on the cable it should be placed at the end of the cable. If a second drive is placed on the
same cable it should be placed on the next closest connector to the end of the cable (6” away
from the end of the cable).
•
Grounding: Provide a direct low impedance chassis path between the motherboard ground
and hard disk drives.
•
UltraATA/66: Ultra ATA/66 requires the use of an 80 conductor cable
•
ICH Placement: The ICH should be placed within 8” of the ATA connector.
•
PC99 Requirement: Support Cable Select for master-slave configuration is a system design
requirement for Microsoft* PC99. The CSEL signal needs to be pulled down at the host side
by using a 470
Ω
pull-down resistor for each ATA connector.
A new IDE cable is required for Ultra ATA/66. This cable is an 80 conductor cable; however, the
40 pin connectors do not change. The wires in the cable alternate: ground, signal, ground, signal,
ground, signal, ground, etc. All the ground wires are tied together on the cable (and they are tied to
Figure 4-15. IDE Min/Max Routing and Cable Lengths
10-18 in.
4-6 in.
5-12 in.
8 in. Max
I C H
I D E
C o n n e c t o r
T r a c e s
Summary of Contents for 810A3
Page 1: ...Intel 810A3 Chipset Platform Design Guide July 2000 Order Number 298186 002...
Page 11: ...1 Introduction...
Page 12: ...This page is intentionally left blank...
Page 25: ...2 PGA370 Processor Design Guidelines...
Page 26: ...This page is intentionally left blank...
Page 41: ...3 SC242 Processor Design Guidelines...
Page 42: ...This page is intentionally left blank...
Page 51: ...4 Layout and Routing Guidelines...
Page 52: ...This page is intentionally left blank...
Page 93: ...5 Advanced System Bus...
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Page 115: ...6 Clocking...
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Page 123: ...7 System Design Considerations...
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Page 137: ...8 Design Checklist...
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Page 157: ...9 Third Party...
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Page 163: ...A PCI Devices Functions Registers Interrupts...