Advanced System Bus Design
5-18
Intel
®
810A3 Chipset Design Guide
5.4
Definitions of Flight Time Measurements/
Corrections and Signal Quality
Acceptable signal quality must be maintained over all operating conditions to ensure reliable
operation. Signal Quality is defined by four parameters: Overshoot, Undershoot, Settling Limit,
and Ringback. Timings are measured at the pins of the driver and receiver, while signal integrity is
observed at the receiver chip pad. When signal integrity at the pad violates the following guidelines
and adjustments need to be made to flight time, the adjusted flight time obtained at the chip pad can
be assumed to have been observed at the package pin, usually with a small timing error penalty.
5.4.1
V
REF
Guardband
To account for noise sources that may affect the way an AGTL+ signal becomes valid at a receiver,
V
REF
is shifted by
∆
V
REF
for measuring minimum and maximum flight times. The V
REF
Guardband region is bounded by V
REF
-
∆
V
REF
and V
REF
+
∆
V
REF.
∆
V
REF
has a value of 100 mV,
which accounts for the following noise sources:
•
Motherboard coupling
•
V
TT
noise
•
V
REF
noise
5.4.2
Ringback Levels
The example topology covered in this guideline assumes ringback tolerance allowed to within
200 mV of 2/3 V
TT
. Since V
TT
is specified with approximate total ±11% tolerance, this implies a
2/3 V
TT
(V
REF
) range from approximately 0.89 V to 1.11 V. This places the absolute ringback
limits at:
•
1.3 V (1.1 V + 200 mV) for rising edge ringback
•
0.69 V (0.89 V – 200 mV) for falling edge ringback
A violation of these ringback limits requires flight time correction as documented in the Intel
®
Pentium
®
II Processor Developer’s Manual.
5.4.3
Overdrive Region
The overdrive region is the voltage range, at a receiver, from V
REF
to V
REF
+ 200 mV for a low-to-
high going signal and V
REF
to V
REF
- 200 mV for a high-to-low going signal. The overdrive
regions encompass the V
REF
Guardband. So, when V
REF
is shifted by
∆
V
REF
for timing
measurements, the overdrive region does not shift by
∆
V
REF
.
Figure 5-10
depicts this relationship.
Corrections for edge rate and ringback are documented in the Intel
®
Pentium
®
II Processor
Developer’s Manual. However, there is an exception to the documented correction method. The
Intel
®
Pentium
®
II Processor Developer’s Manual states that extrapolations should be made from
the last crossing of the overdrive region back to V
REF
. Simulations performed on this topology
should extrapolate back to the appropriate V
REF
Guardband boundary, and not V
REF
. So, for
maximum rising edge correction, extrapolate back to V
REF
+
∆
V
REF
. For maximum falling edge
corrections, extrapolate back to V
REF
-
∆
V
REF
.
Summary of Contents for 810A3
Page 1: ...Intel 810A3 Chipset Platform Design Guide July 2000 Order Number 298186 002...
Page 11: ...1 Introduction...
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Page 25: ...2 PGA370 Processor Design Guidelines...
Page 26: ...This page is intentionally left blank...
Page 41: ...3 SC242 Processor Design Guidelines...
Page 42: ...This page is intentionally left blank...
Page 51: ...4 Layout and Routing Guidelines...
Page 52: ...This page is intentionally left blank...
Page 93: ...5 Advanced System Bus...
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Page 115: ...6 Clocking...
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Page 123: ...7 System Design Considerations...
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Page 137: ...8 Design Checklist...
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Page 157: ...9 Third Party...
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Page 163: ...A PCI Devices Functions Registers Interrupts...