Intel 810A3, Design Manual

Page: 110 / 166

Advanced System Bus Design
5-16 Intel
®
810A3 Chipset Design Guide
When routing and stackup constraints require that an AGTL+ signal reference VCC or multiple
planes, special care must be given to minimize the SSO impact to timing and noise margin. The
best method of reducing adverse effects is to add high-frequency decoupling wherever the
transitions occur, as shown in
Figure 5-8 and Figure 5-9 . Such decoupling should, again, be in the
vicinity of the signal transition via and use capacitors with minimal effective series resistance
(ESR) and effective series inductance (ESL). When placing the caps it is recommended to space
the VSS and VCC vias as close as possible and/or use dual vias since the via inductance may
sometimes be higher than the actual capacitor inductance.
5.3.3.3 High Frequency Decoupling
This section contains several high frequency decoupling recommendations that will improve the
return path for an AGTL+ signal. These design recommendations will very likely reduce the
amount of SSO effects.
Just as layer switching and multiple reference planes can create discontinuities in an AGTL+ signal
return path, discontinuities may also occur when a signal transitions between the baseboard and
cartridge. Therefore, providing adequate high-frequency decoupling across VCC
CORE
and ground
at the SC242 connector interface on the baseboard will minimize the discontinuity in the signal’s
reference plane at this junction. Note that these additional high-frequency decoupling capacitors
are in addition to the high-frequency decoupling already on the processor.
Transmission line geometry also influences the return path of the reference plane. The following
are decoupling recommendations that take this into consideration:
•
A signal that transitions from a stripline to another stripline should have close proximity
decoupling between all four reference planes.
•
A signal that transitions from a stripline to a microstrip (or vice versa) should have close
proximity decoupling between the three reference planes.
•
A signal that transitions from a stripline or microstrip through vias or pins to a component
(GMCH, etc.) should have close proximity decoupling across all involved reference planes to
ground for the device.
Figure 5-8. Layer Switch with Multiple Reference Planes
Figure 5-9. One Layer with Multiple Reference Planes
Signal Layer A
Ground Plane
Power Plane
Signal Layer B
Layer
Layer
G r o u n d
Signal Layer A
P o w e r