Intel 810A3, Design Manual

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Design Checklist
8-12 Intel
®
810A3 Chipset Design Guide
Table 8-18. Clock Generator Checklist
Checklist Line Items Comments
VDD3 Pins
Each of the following groups of pins (all belonging to VDD3) need to be on their own
isolated 3.3V power plane:
Group 1: VCC3 pins 2, 9, 10 and 21
Group 2: VCC3 pin 27
Group 3: VCC3 pins 33, 38 and 44 (also SEL1)
CPU Series resistor 33
Ω
± 5%.
SDRAM Series resistor 22 ohm ± 5%.
DCLK
Series resistor 33
Ω
± 5%.
DCLK cap: 22 pF ± 2%
3V66
Series resistor 22
Ω
± 5%.
3V66 cap: 18 pF ± 2%
PCI Series resistor 33
Ω
± 5%.
TCLK Series resistor 22
Ω
± 5%.
OCLK/RCLK Series resistor 33
Ω
± 5%.
48 MHz Series resistor 33
Ω
± 5%.
APIC Series resistor 33
Ω
± 5%.
REF Series resistor 10
Ω
± 5%.
Table 8-19. FWH Flash BIOS Checklist
Checklist Line Items Comments
No floating inputs. Unused FGPI pins need to be tied to a valid logic level.
INIT# FWH Flash BIOS INIT# must be connected to processor INIT#.
RST# FWH Flash BIOS RST# must be connected to PCIRST#.
ID[3:0] For a system with only one FWH Flash BIOS device, tie ID[3:0] to ground.
Table 8-20. PCI Bus Checklist
Checklist Line Items Comments
ACK64#
REQ64#
(5V PCI environment) 2.7 K
Ω
(approximate) pull-up resistors to VCC5.
(3V PCI environment) 8.2 K
Ω
(approximate) pull-up resistors to VCC3_3.
Each REQ64# and ACK64# requires its own pull-up.
IDSEL lines to PCI
connectors
100
Ω
series resistor.
SBO#
SDONE
5.6 K
Ω
pull-up resistor to VCC3_3 or VCC5.
3Vaux Optional to 3VSB, but required if PCI devices supporting wakeup events.