Intel 810A3, Design Manual

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Intel
®
810A3 Chipset Design Guide 4-13
Layout and Routing Guidelines
the ground on the motherboard through the ground pins in the 40 pin connector). This cable
conforms to the Small Form Factor Specification SFF-8049. This specification can be obtained
from the Small Form Factor Committee.
Motherboard
•
ICH Placement: The ICH should be placed within 8” of the ATA connector(s). There are no
minimum length requirements for this spacing.
•
Capacitance: The capacitance of each pin of the IDE connector on the host should be below
25 pF when the cables are disconnected from the host.
•
Series Termination: There is no need for series termination resistors on the data and control
signals since there is series termination integrated into these signal lines on the ICH.
— A 1 K
Ω
pullup to 5V is required on PIORDY and SIORDY.
— A 470
Ω
pulldown is required on pin 28 of each connector.
— A 5.6 K
Ω
pulldown is required on PDREQ and SDREQ.
— Support Cable Select (CSEL) is a PC99 requirement. The state of the cable select pin
determines the master/slave configuration of the hard drive at the end of the cable.
— Primary IDE connector uses IRQ14 and the secondary IDE connector uses IRQ15.
— IRQ14 and IRQ15 each need an 8.2 K
Ω
pull-up resistor to VCC.
— Due to the elimination of the ISA bus from the ICH, PCI_RST# should be connected to
pin 1 of the IDE connectors as the IDE reset signal. Due to high loading, the PCI_RST#
signal should be buffered.
— There is no internal pull up or down on PDD7 or SDD7 of the ICH. Devices shall not have
a pull-up resistor on DD7. It is recommended that a host have a 10 K
Ω
pull-down resistor
on PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up (as
required by the ATA-4 specification).
— If no IDE is implemented with the ICH, the input signals (xDREQ and xIORDY) can be
grounded and the output signals left as no connects.
Figure 4-16. Ultra ATA/66 Cable
IDE Connector
Black wires are ground
Grey wires are signals