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PGA370 Processor Design Guidelines

2-2

Intel

®

810A3 Chipset  Design Guide

2.2

PGA370 Socket Definition Details

The following tables compare legacy pin names and functions to new flexible pin names and 
functions. Designers need to pay close attention to the notes section for this table for compatibility 
concerns regarding these pin changes.

Table 2-1. Platform Pin Definition Comparison for Single Processor Designs

Pin #

Legacy

PGA370 

pin name

Flexible

PGA370

pin name

Function

Type

Notes

A29

Reserved

DEP7#

Data bus ECC data

AGTL+, I/O

2

A31

Reserved

DEP3#

Data bus ECC data

AGTL+, I/O

2

A33

Reserved

DEP2#

Data bus ECC data

AGTL+, I/O

2

AC1

Reserved

A33#

Additional AGTL+ address

AGTL+, I/O

2

AC37

Reserved

RSP#

Response parity

AGTL+, I

2

AF4

Reserved

A35#

Additional AGTL+ address

AGTL+, I/O

2

AH20

Reserved

VTT

AGTL+ termination voltage

Power

AH4

Reserved

RESET#

Processor reset (Intel

®

 

Pentium

®

 III)

AGTL+, I

3

AJ31

GND

BSEL1

System bus frequency select

CMOS, I/O

1

AK16

Reserved

VTT

AGTL+ termination voltage

Power

AK24

Reserved

AERR#

Address parity error 

AGTL+, I/O

2

AL11

Reserved

AP0#

Address parity

AGTL+, I/O

2

AL13

Reserved

VTT

AGTL+ termination voltage

Power

AL21

Reserved

VTT

AGTL+ termination voltage

Power

AM2

GND

Reserved

Reserved

Reserved

1

AN11

Reserved

VTT

AGTL+ termination voltage

Power

AN13

Reserved

AP1#

Address parity

AGTL+, I/O

2

AN15

Reserved

VTT

AGTL+ termination voltage

Power

AN23

Reserved

RP#

Request parity

AGTL+, I/O

B36

Reserved

BINIT#

Bus initialization

AGTL+, I/O

2

C29

Reserved

DEP5#

Data bus ECC data

AGTL+, I/O

2

C31

Reserved

DEP1#

Data bus ECC data

AGTL+, I/O

2

C33

Reserved

DEP0#

Data bus ECC data

AGTL+, I/O

2

E29

Reserved

DEP6#

Data bus ECC data

AGTL+, I/O

2

E31

Reserved

DEP4#

Data bus ECC data

AGTL+, I/O

2

G35

Reserved

VTT

AGTL+ termination voltage

Power

V4

Reserved

BERR#

Bus error

AGTL+, I/O

2

W3

Reserved

A34#

Additional AGTL+ address

AGTL+, I/O

2

X4

RESET#

RESET2#

Processor reset (Value 
processors)

AGTL+, I

3

X6

Reserved

A32#

Additional AGTL+ address

AGTL+, I/O

2

Y33

GND

CLKREF

1.25V PLL reference

Power

1

Summary of Contents for 810A3

Page 1: ...Intel 810A3 Chipset Platform Design Guide July 2000 Order Number 298186 002...

Page 2: ...ime without notice Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order The Intel 810A3 Chipset may contain design defect...

Page 3: ...5 CLKREF Circuit Implementation 2 10 2 2 6 Undershoot Overshoot Requirements 2 10 2 2 7 Connecting RESET and RESET2 on a Flexible PGA370 Design 2 11 2 2 8 Reset Strapping Options 2 11 2 2 9 Voltage Re...

Page 4: ...Considerations 4 26 4 13 4 RTC External Battery Connection 4 26 4 13 5 RTC External RTCRESET Circuit 4 27 4 13 6 VBIAS DC Voltage and Noise Measurements 4 27 4 14 Processor PLL Filter Recommendation 4...

Page 5: ...ock Architecture 6 2 6 3 Clock Routing Guidelines 6 3 6 4 Capacitor Sites 6 6 6 5 Clock Power Decoupling Guidelines 6 6 7 System Design Considerations 7 1 7 1 Power Delivery 7 1 7 1 1 Intel 810A3 Chip...

Page 6: ...ystem Memory Connectivity 4 7 4 8 Display Cache Topology 1 4 7 4 9 Display Cache Topology 2 4 8 4 10 Display Cache Topology 3 4 8 4 11 Display Cache Topology 4 4 9 4 12 Hub Interface Signal Routing Ex...

Page 7: ...Reference Plane 5 15 5 7 Layer Switch with Multiple Reference Planes same type 5 15 5 8 Layer Switch with Multiple Reference Planes 5 16 5 9 One Layer with Multiple Reference Planes 5 16 5 10 Overdri...

Page 8: ...4 8 4 5 Display Cache Routing Topology 4 4 9 4 6 AC 97 Configuration Combinations 4 18 4 7 Recommended USB Trace Characteristics 4 23 4 8 Inductor 4 30 4 9 Capacitor 4 30 4 10 Resistor 4 30 4 11 DPLL...

Page 9: ...I Bus Checklist 8 12 8 21 USB Keyboard Mouse Checklist 8 13 8 22 AC 97 Checklist 8 13 8 23 Power Delivery Checklist 8 14 9 1 Super I O 9 1 9 2 Clock Generation 9 1 9 3 Memory Vendors 9 1 9 4 Voltage R...

Page 10: ...x Intel 810A3 Chipset Design Guide Revision History Revision Description Date 001 Initial Release April 2000 002 Minor edits throughout for clarity Added Section 7 2 4 Ground Flood Plane July 2000...

Page 11: ...1 Introduction...

Page 12: ...This page is intentionally left blank...

Page 13: ...ences of related documents This chapter also provides an overview of the Intel 810A3 chipset Chapter 2 PGA370 Processor Design Guidelines This chapter provides design guidelines for the PGA370 process...

Page 14: ...le Edge Connector S E C cartridge contains 56 pull up resistors to provide termination at each bus load Bus Agent A component or group of components that when combined represent a single load on the A...

Page 15: ...tion that the victim is switching Odd Mode Cross talk coupling from multiple aggressors when all the aggressors switch in the opposite direction that the victim is switching Derived power rail A deriv...

Page 16: ...oltage and manufacturing process Some less obvious causes include effects of Simultaneous Switching Output SSO and packaging effects The Maximum Flight Time is the largest flight time a network will e...

Page 17: ...Setup Window Is the time between the beginning of Setup to Clock TSU_MIN and the arrival of a valid clock edge This window may be different for each type of bus agent in the system Simultaneous Switch...

Page 18: ...ding interconnect branches terminating at agent pads Undershoot Maximum voltage allowed for a signal to extend below VSS at the processor core pad See the respective Processor s Electrical Mechanical...

Page 19: ...erview The Intel 810A3 chipset is the first generation Integrated Graphics chipset designed for the Intel CeleronTM processor The graphics accelerator architecture consists of dedicated multi media en...

Page 20: ...ssor product line The Intel Celeron processor PPGA implements a Dynamic Execution micro architecture and executes MMXTM media technology instructions for enhanced media and communication performance T...

Page 21: ...interface AC 97 2 1 interface Integrated System Management Controller Alert on LAN Interrupt controller 1 2 3 System Configurations Figure 1 1 Intel 810A3 Chipset System Bus 66 100 MHz System Memory...

Page 22: ...CO Timer This timer is used to detect system locks The first expiration of the timer generates an SMI which the system can use to recover from a software lock The second expiration of the timer causes...

Page 23: ...mation is communicated over the AC link Microphone input and left and right audio channels are supported for a high quality two speaker audio solution Wake on ring from suspend is also supported with...

Page 24: ...vides for two joysticks and a two wire MPU 401 MIDI interface Consult your preferred Super I O vendor for a comprehensive list of devices offered and features supported In addition depending on system...

Page 25: ...2 PGA370 Processor Design Guidelines...

Page 26: ...This page is intentionally left blank...

Page 27: ...lity In general these designs support 66 100 MHz bus operation for the Intel 810A3 chipset and 66 100 133 MHz host bus operation for the Intel 810E chipset VRM 8 4 DC DC Converter Guidelines and Intel...

Page 28: ...1 GND BSEL1 System bus frequency select CMOS I O 1 AK16 Reserved VTT AGTL termination voltage Power AK24 Reserved AERR Address parity error AGTL I O 2 AL11 Reserved AP0 Address parity AGTL I O 2 AL13...

Page 29: ...Data bus ECC data AA33 Reserved Reserved VTT AGTL termination voltage AA35 Reserved Reserved VTT AGTL termination voltage AC1 Reserved Reserved A33 Additional AGTL address AC37 Reserved Reserved RSP...

Page 30: ...mbers in table are for reference only These timing parameters are subject to change Check the appropriate component documentation for valid timing parameter values 3 TSU_MIN 2 72 ns assumes the GMCH s...

Page 31: ...served when multiple bits are switching simultaneously These multi bit effects can adversely affect flight time and signal quality and are sometimes not accounted for in simulation Accordingly maximum...

Page 32: ...of at least 2 1 1 for microstrip geomety If r 4 5 this should limit coupling to 3 4 For example intragroup AGTL routing could use 10 mil spacing 5 mil traces and a 5 mil prepreg between the signal lay...

Page 33: ...nd their corresponding control lines Additional Considerations Distribute VTT with a wide trace A 0 050 minimum trace is recommended to minimize DC losses Route the VTT trace to all components on the...

Page 34: ...e these traces parallel 0 5 Layer route both on the same layer Table 2 8 Routing Guidelines for Non AGTL Signals Signal Trace Width Spacing to Other Traces Trace Length A20M 5 mils 10 mils 1 to 9 FERR...

Page 35: ...gnal is still connected to the PGA370 socket the Intel Pentium III processor does not utilize it Only the Intel Celeron processor PPGA utilizes the BSEL0 signal The Intel Pentium III processors are 3...

Page 36: ...tipulate that a signal at the output of the driver buffer and at the input of the receiver buffer must not exceed a maximum absolute overshoot voltage limit 2 1V and a minimum absolute undershoot volt...

Page 37: ...I processors using a 370 pin socket RESET is delivered to both pins X4 and AH4 2 2 8 Reset Strapping Options LMD26 on the GMCH is used as a strap at reset to determine whether the system board is supp...

Page 38: ...processor at speeds greater than 650 MHz has changed from previous processors Transient and static tolerances are tighter than VRM 8 2 Additional motherboard decoupling required to meet VRM 8 4 2 2 10...

Page 39: ...EF pins within 500 mils 2 2 11 Thermal EMI Differences Heatsink requirements will be different for FC PGA processors from previous processors using PPGA packaging Refer to the processor datasheet for...

Page 40: ...it into the same printed circuit board layout Just the pin numbers would change as can be seen in the drawing below Caution The Intel Pentium III processor requires an in target probe ITP with a 1 5V...

Page 41: ...3 SC242 Processor Design Guidelines...

Page 42: ...This page is intentionally left blank...

Page 43: ...hanical and Thermal Specification and appropriate Intel 810A3 chipset component specification NOTES 1 All times in nanoseconds 2 Numbers in table are for reference only These timing parameters are sub...

Page 44: ...rdingly maximum flight times depend on the baseboard design and additional adjustment factors or margins are recommended SO push out or pull in Rising or falling edge rate degradation at the receiver...

Page 45: ...references assuming a 4 layer motherboard design The trace width is recommended to be 5 mils and not greater than 6 mils Table 3 5 contains the trace width space ratios assumed for this topology The c...

Page 46: ...als Route AGTL address data and control signals in separate groups to minimize crosstalk between groups The Pentium III processor uses a split transaction bus In a given clock cycle the address lines...

Page 47: ...tt trace to all components on the host bus Be sure to include decoupling capacitors Guidelines for Vtt distribution and decoupling are contained in AP 907 Pentium III Processor Power Distribution Guid...

Page 48: ...ncy Select for SC242 Designs Figure 3 3 shows the GMCH and processor straps for selecting the system bus frequency Figure 3 3 System Bus Frequency Selection Topology for SC242 GMCH LMD29 LMD13 SEL0 SE...

Page 49: ...rd are discussed in detail further in this section The reference design GRM is asymmetric and requires 0 159 mounting holes To minimize the impact to trace routing only two ground pads are required Th...

Page 50: ...er of the board and possibly short out traces immediately beneath the solder mask resulting in board failure The required thickness of the pad is less than 0 001 using 1 2 oz copper Figure 3 5 Detaile...

Page 51: ...4 Layout and Routing Guidelines...

Page 52: ...This page is intentionally left blank...

Page 53: ...ted i e 60 15 is the nominal trace impedance for a 5 mil wide trace i e the impedance of the trace when not subjected to the fields created by changing current in neighboring traces When calculating f...

Page 54: ...GMCH Quadrant Layout topview Component Side Layer 1 1 2 oz cu Power Plane Layer 2 1 oz cu Ground Layer 3 1 oz cu Solder SIde Layer 4 1 2 oz cu 4 5 mil Prepreg 4 5 mil Prepreg 48 mil Core 62 mils Tota...

Page 55: ...Intel 810A3 Chipset Design Guide 4 3 Layout and Routing Guidelines Figure 4 3 ICH 241 uBGA Quadrant Layout topview PCI Pin 1 Corner Processor Hub Interface ICH 241 uBGA IDE LPC AC 97 SMBus...

Page 56: ...ntel 810A3 Chipset Design Guide 4 4 Intel 810A3 Chipset Component Placement The assumptions for component placement are uATX Form Factor 4 Layer Motherboard Single Sided Assembly Figure 4 4 uATX Place...

Page 57: ...ce mils A B C D E F G Signal Top Width Space Max Min Max Min Max Min Max Min Max Min Max Min Max SCS 3 2 Opt 1 5 10 8 3 5 1 5 2 Opt 2 5 10 8 2 2 5 1 5 1 8 Opt 3 5 10 8 1 6 5 1 15 1 5 SCS 1 0 Opt 1 4 1...

Page 58: ...Layout and Routing Guidelines 4 6 Intel 810A3 Chipset Design Guide 4 5 2 System Memory Routing Example Figure 4 6 System Memory Routing Example...

Page 59: ...ectivity Figure 4 8 Display Cache Topology 1 SCS 3 2 SCS 1 0 SCKE0 SCKE1 SRAS SCAS S W E SBS 1 0 SMAA 11 8 3 0 SMAA 7 4 SMAB 7 4 SDQM 7 0 SMD 63 0 DIMM_CLK 3 0 DIMM_CLK 7 4 SMB_CLK SMB_DATA System Mem...

Page 60: ...e 4 9 Display Cache Topology 2 Table 4 3 Display Cache Routing Topology 2 Trace units mils B inches C inches Signal Topology Width Spacing Min Max Min Max LMA 11 0 LWE LCS LRAS LCAS 2 5 7 1 3 75 0 75...

Page 61: ...Strobe Signals HL_STB HL_STB differential strobe pair There are no pull ups or pull downs required on the hub interface HL11 can be brought out to a test point for NAND Tree testing Each signal should...

Page 62: ...he trace length for each data signal should be matched to the trace length of the strobes with 0 1 4 7 3 HREF Generation Distribution There are two types of HREF generation For a single hub interface...

Page 63: ...trace targeted for a nominal trace impedance of 40 ZCOMP The HLCOMP pin should be tied to a 10 mil trace that is AT LEAST 18 long This trace should be unterminated and care should be taken when routi...

Page 64: ...maximum of 6 inches between drive connectors on the cable If a single drive is placed on the cable it should be placed at the end of the cable If a second drive is placed on the same cable it should b...

Page 65: ...5 6 K pulldown is required on PDREQ and SDREQ Support Cable Select CSEL is a PC99 requirement The state of the cable select pin determines the master slave configuration of the hard drive at the end o...

Page 66: ...PDD 15 8 PDD 6 0 PCIRST_BUF 22 47 ohm PDA 2 0 PDCS1 PDCS3 PDIOR PDIOW PDDREQ PIORDY PDD 7 Due to high loading PCIRST must be buffered 1k ohm 5V 470 ohm CSEL Pin32 N C PDDACK IRQ14 5V 8 2k ohm 5 6k ohm...

Page 67: ...n only enable modes that do not require an 80 conductor cable example Ultra ATA 33 Mode After determining the Ultra DMA mode to be used the BIOS will configure the Intel 810A3 chipset hardware and sof...

Page 68: ...eleasing it In an 80 conductor cable PDIAG CBLID is not connected through and therefore the capacitor has no effect In a 40 conductor cable PDIAG CBLID is connected though to the drive Therefore the s...

Page 69: ...1 shows the layout that allows for both host side and drive side detection For Host Side Detection R1 is a 0 resistor R2 is a 15 K resistor C1 is not stuffed For Drive Side Detection R1 is not stuffed...

Page 70: ...link For example if an AMC is on the link it must be the only codec If an AC is on the link another AC cannot be present 4 9 1 Audio Modem Riser Card AMR Intel is developing a common connector specifi...

Page 71: ...nalog audio ground plane from the rest of the board ground plane There should be a single point to wide where the analog isolated ground plane connects to the main ground plane The split between the p...

Page 72: ...s used as the timebase for latching and driving data The ICH supports wake on ring from S1 S4 via the AC 97 link The codec asserts SDATAIN to wake the system To provide wake capability and or caller I...

Page 73: ...ts Wake On Ring from S1 S4 states via the AC 97 link The codec asserts SDATAIN to wake the system To provide wake capability and or caller ID standby power must be provided to the modem codec If no co...

Page 74: ...or source termination of the reflected signal 47 pF caps must be placed as close to the ICH as possible and on the ICH side of the series resistors on the USB data lines P0 P1 These caps are for signa...

Page 75: ...onnected from the clock generator to the PICCLK pin on the processor Tie PICD0 to VCCCMOS through a 150 resistor Tie PICD1 to VCCCMOS through a 150 resistor Note If not using IOAPIC turn off APIC cloc...

Page 76: ...ots that should be connected to the ICH This limit is due to timing and loading considerations established during simulations If a system designer wants to have 5 PCI slots connected to the ICH then i...

Page 77: ...maintain the RTC accuracy the external capacitor C1 should be set to 0 047 uF and the external capacitor values C2 and C3 should be chosen to provide the manufacturer s specified load capacitance Cloa...

Page 78: ...lated by dividing the capacity by the average current required For example if the battery storage capacity is 170 mA per hour assumed usable and the average current required is 3 uA the battery life w...

Page 79: ...the RTC well to be powered by the battery when the system power is not available Figure 4 28 is an example of this circuitry that is used in conjunction with the external diode circuit 4 13 6 VBIAS D...

Page 80: ...s associated with each component 4 14 3 Filter Specification The function of the filter is to protect the PLL from external noise through low pass attenuation In general the low pass description forms...

Page 81: ...ents Filter should support DC current 30 mA Shielded type inductor to minimize magnetic pickup DC voltage drop from VCC to PLL1 should be 60mV which in practice implies series R 2 also means pass band...

Page 82: ...routing requirements C should be close to PLL1 and PLL2 pins 0 1 per route These routes do not count towards the minimum damping R requirement PLL2 route should be parallel and next to PLL1 route min...

Page 83: ...s represent package routing1 2 120 pF capacitor represents internal decoupling capacitor 3 1 K resistor represents small signal PLL resistance 4 Be sure to include all component and routing parasitics...

Page 84: ...tors and a ferrite bead with a 75 impedance at 100 MHz The LC pi filter is designed to filter glitches produced by the RAMDAC while maintaining adequate edge rates to support high end display resoluti...

Page 85: ...ent Therefore the unit current or LSB current of the DAC signals equals 73 2 A The reference circuitry generates a voltage across this Rset resistor equal to a bandgap voltage divided by three 409 mV...

Page 86: ...GREEN Blue VSSDACA Analog Power Plane 1 8V IREF IWASTE Place the Reference Resistor in Close Proximity to the IREF Pin Rset VGA 1 8V Board Power Plane Rt D2 D1 C1 C2 FB pi Filter Red Route 37 5 Route...

Page 87: ...is recommended for the display PLL analog power supply designed to attenuate power supply noise with frequency content from 100 KHz and above so that jitter amplification is minimized Figure 4 37 is a...

Page 88: ...equal to or less than 3 3 This larger dc resistance tolerance improves the damping and the filter response 4 16 1 Filter Specification The low pass filter specification with the input being the board...

Page 89: ...A ball is 0 1 The VSSDA ball should via straight down to the board ground plane The filter inductor should be placed in close proximity to the filter capacitor and any routing resistance should be ins...

Page 90: ...In addition different values for the resistance of the inductor were assumed based on its max and typical DC resistance This is summarized in Table 4 13 This yielded the four different frequency resp...

Page 91: ...E RIND increases the filter response i e attenuation in PLL bandwidth improves There is a limit of 3 3 total series resistance of the filter to limit DC voltage drop Table 4 13 Resistance Values for F...

Page 92: ...Layout and Routing Guidelines 4 40 Intel 810A3 Chipset Design Guide This page is intentionally left blank...

Page 93: ...5 Advanced System Bus...

Page 94: ...This page is intentionally left blank...

Page 95: ...se components The guideline recommended in this section is based on experience developed at Intel while developing many different Intel Pentium Pro processor family and Intel Pentium III processor bas...

Page 96: ...cation1 TSU_MIN is the minimum required time specified to setup before the clock1 CLKJITTER is the maximum clock edge to edge variation CLKSKEW is the maximum variation between components receiving th...

Page 97: ...can be reduced Intel recommends running simulations at the device pads for signal quality and at the device pins for timing analysis However simulation results at the device pins may be used later to...

Page 98: ...662 mil2 inch value for annealed copper that is published in reference material Using the 1 mil2 inch value may increase the accuracy of lossy simulations Positioning drivers with faster edges closer...

Page 99: ...lock skew to a minimum clock buffers that allow their outputs to be tied together are recommended Intel strongly recommends running analog simulations to ensure that each design has adequate noise and...

Page 100: ...out for both 1 and 2 way 133 MHz 100 MHz processor Intel 810A3 chipset systems Power distribution and chassis requirements for cooling connector location memory location etc may constrain the system t...

Page 101: ...er begins its next transition Intersymbol Interference ISI occurs when transitions in the current cycle interfere with transitions in subsequent cycles ISI can occur when the line is driven high low a...

Page 102: ...quality is at the pad of the component The expected method of determining the signal quality is to run analog simulations for the pin and the pad Then correlate the simulations at the pin against act...

Page 103: ...be generated using the same test load for TCO Intel provides this timing value in the AGTL I O buffer models In this manner the following valid delay equation is satisfied Equation 5 5 Valid Delay Equ...

Page 104: ...vershoot Undershoot specifications Settling Limit 5 2 2 Timing Requirements The system timing for AGTL is dependent on many things Each of the following elements combine to determine the maximum and m...

Page 105: ...s in a direction opposite that of the aggressor s signal Forward cross talk creates a signal that propagates in the same direction as the aggressor s signal On the AGTL bus a driver on the aggressor n...

Page 106: ...half of the rise time of the aggressor s signal Assuming the ideal ramp on the aggressor from 0 to 100 voltage swing and the fall time on an unloaded coupled network then An example calculation follow...

Page 107: ...ters These equations are Equation 5 6 Intrinsic Impedance Equation 5 7 Stripline Intrinsic Propagation Speed ns ft Equation 5 8 Microstrip Intrinsic Propagation Speed ns ft Equation 5 9 Effective Prop...

Page 108: ...on an external layer using an adjacent plane for reference with solder mask and air on the other side of the trace This is in part due to the difficulty of precise control of the dielectric constant o...

Page 109: ...the ideal case where a particular signal is routed entirely within the same signal layer with a ground layer as the single reference plane When it is not possible to route the entire AGTL signal on a...

Page 110: ...return path discontinuities may also occur when a signal transitions between the baseboard and cartridge Therefore providing adequate high frequency decoupling across VCCCORE and ground at the SC242 c...

Page 111: ...for the example topology given in this document have a total clock skew of 200 ps and 150 ps of clock jitter For a given design the clock distribution system including the clock components must be eva...

Page 112: ...ed to within 200 mV of 2 3 VTT Since VTT is specified with approximate total 11 tolerance this implies a 2 3 VTT VREF range from approximately 0 89 V to 1 11 V This places the absolute ringback limits...

Page 113: ...ments for a falling edge are taken at the VREF VREF crossing and maximum flight time is taken at the VREF VREF crossing 5 5 Conclusion AGTL routing requires a significant amount of effort Planning ahe...

Page 114: ...Advanced System Bus Design 5 20 Intel 810A3 Chipset Design Guide This page is intentionally left blank...

Page 115: ...6 Clocking...

Page 116: ...This page is intentionally left blank...

Page 117: ...P Package 3 copies of processor Clock 66 MHz 100 MHz 2 5V CPU GCH ITP 9 copies of 100 MHz all the time SDRAM Clock 3 3V SDRAM 0 7 DClk 8 copies of PCI Clock 33 MHz 3 3V 2 copies of APIC Clock 16 67 MH...

Page 118: ...SEL0 SDATA SCLK SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 DCLK 32 29 28 30 31 46 45 43 42 40 39 37 36 34 Main Memory 2 DIMMS ITP Processor GMCH Data Address Control 3 3V 3V66_0 USB_0 14...

Page 119: ...d plane Table 6 2 Group Skew and Jitter Limits at the Pins of the Clock Chip Signal Group Pin Pin Skew Cycle Cycle Jitter Nominal Vdd Skew jitter measure point CPU 175 pS 250 pS 2 5V 1 25V SDRAM 250 p...

Page 120: ...oise coupling of memory related signals into the 48 MHz clock signal Table 6 4 Layout Dimensions Group Receiver Resistor Cap Topolog y A B C D SDRAM DIMM 22 N A Layout 1 0 5 X N A N A CPU Segment C PP...

Page 121: ...the different topologies used for the clock routing guidelines Figure 6 2 Different Topologies for the Clock Routing Guidelines Layout 1 B A Layout 2 B C A B D Layout 4 Socket Connector Socket Connec...

Page 122: ...possible and connect with short wide traces and copper Connect pins to appropriate power plane with power vias larger than signal vias Bulk decoupling should be connected to plane with 2 or more power...

Page 123: ...7 System Design Considerations...

Page 124: ...This page is intentionally left blank...

Page 125: ...es via 3 3Vaux the Intel 82559 LAN down chip AC 97 and optionally USB USB can only be powered if sufficient standby power is available To ensure that enough power is available during STR a thorough po...

Page 126: ...10 LPC Super I O 3 3V 0 3V 50mA S0 S1 PS 2 Keyboard Mouse 5V 0 5V 1A S0 S1 Super I O 2 DIMM Slots 3 3VSB 0 3V 4 8A S0 S1 64mA S3 3 PCI 3 3Vaux 3 3VSB 0 3V 1 125A S0 S1 60mA S3 S5 82559 LAN Down 3 3VSB...

Page 127: ...A Display Cache 3 000 3 3 3 600 960 3456 N A N A FWH Flash BIOS Core 3 000 3 3 3 600 67 241 2 N A N A AC 97 3 3V 3 135 3 3 3 465 1000 3465 N A N A GMCH 3 135 3 3 3 465 330 1143 45 N A N A Super I O 3...

Page 128: ...ference Board the only device connected directly to the 5V Dual plane is the 3 3V voltage regulator to regulate to lower voltages VCCCORE This power plane is used to power the processor Refer to the l...

Page 129: ...ull power Operation 375 mA number of PCI slots Suspend Operation 375 20 number of PCI slots 1 The total maximum current requirement for the 3 3VSB power plane as well as the 3 3V regulator is 7 12 A N...

Page 130: ...rs to use keep in mind the operating temperatures that will be seen and the rated tolerance Bulk capacitance with a low Effective Series Resistance ESR should also be placed near the Intel Celeron pro...

Page 131: ...acitors orientation such that flight time will be minimized Vias between GMCH ball and cap pad see Figure 7 2 The use of top side component side capacitors near the GMCH as shown in Figure 7 2 as the...

Page 132: ...ard plane decoupling is significant typically 25 pF sq inch without the ground flood plane vs 225 pF sq inch with the ground flood plane The added board plane decoupling has a much wider frequency spe...

Page 133: ...gnals during different power state transitions Figure 7 3 G3 S0 Transistion Clocks invalid Clocks valid t17 t16 t15 t14 t13 t12 t10 t11 t9 t8 t7 t6 t5 t4 t3 t2 t1 Vcc3 3sus RSMRST SLP_S3 SLP_S5 SUS_ST...

Page 134: ...locks valid Clocks invalid Clocks valid t16 t15 t9 t22 t8 t23 t21 t17 t13 t12 t11 t20 t19 t7 t18 t24 Vcc3 3sus RSMRST STPCLK Stop Grant Cycle CPUSLP Go_C3 from ICH Ack_C3 from GMCH DRAM SUS_STAT PCIRS...

Page 135: ...s valid Clocks invalid Clocks valid t16 t15 t9 t22 t8 t26 t25 t23 t21 t17 t13 t12 t11 t20 t19 t7 t18 t24 Vcc3 3sus RSMRST STPCLK Stop Grant Cycle CPUSLP Go_C3 from ICH Ack_C3 from GMCH DRAM SUS_STAT P...

Page 136: ...RST inactive 500 us t11 PWROK active to PCIRST inactive 9 1 1 ms t12 PCIRST inactive to Cycle 1 from GMCH 1 ms t13 Cycle 1 from ICH to Cycle 2 from GMCH 60 ns t14 PCIRST inactive to STPCLK de assertio...

Page 137: ...8 Design Checklist...

Page 138: ...This page is intentionally left blank...

Page 139: ...sign will function properly Beyond the items contained in the following text refer to the most recent version of the Design Guide for more detailed instructions on designing a motherboard 8 1 1 Design...

Page 140: ...onnect not supported by chipset BERR I O Leave as No Connect not supported by chipset BINIT I O Leave as No Connect not supported by chipset BNR 1 I O Connect to GMCH BP 3 2 I O Leave as No Connect BP...

Page 141: ...hipset IGNNE I 150 pullup resistor to VCCCMOS Connect to ICH INIT I 150 pullup resistor to VCCCMOS Connect to ICH FWH Flash BIOS LINT0 INTR I 150 pullup resistor to VCCCMOS Connect to ICH LINT1 NMI I...

Page 142: ...ed on motherboard Typically a 4 7 uH inductor in series with VCCCORE is connected to PLL1 then through a series 33 uF capacitor to PLL2 RTTCTRL5 S35 110 1 pulldown resistor to ground SLEWCTRL E27 110...

Page 143: ...ecklist for SC242 Processors CPU Pin I O Comments A 35 3 1 I O Connect A 31 3 to GMCH Leave A 35 32 as No Connect not supported by chipset ADS 1 I O Connect to GMCH AERR I O Leave as No Connect not su...

Page 144: ...leave as No Connect Table 8 7 TAP Checklist for SC242 Processors CPU Pin I O Comments TCK I 1K pullup resistor to VCC_2 5 47 series resistor to ITP TDI I 200 330 pullup resistor to VCC_2 5 Connect to...

Page 145: ...VR 10 K pullup resistor to power solution compatible voltage required usually pulled up to input voltage of the VR Some of these solutions have internal pullups Optional override jumpers ASIC etc coul...

Page 146: ...ntegrated series resistors PCIRST The PCIRST signal should be buffered to the IDE connectors No floating inputs including bi directional signals Unused core well inputs should be tied to a valid logic...

Page 147: ...for a nominal trace impedance of 40 Option 2 ZCOMP Method The COMP pin must be tied to a 10 mil trace that is AT LEAST 18 inches long This trace must be un terminated and care should be taken when rou...

Page 148: ...Tri state mode for testing purposes will tri state all signals LMD29 0 System bus frequency 66 MHz 1 System bus frequency 100 MHz LMD28 ThevalueonLMD28sampledattherisingedgeofCPURST reflects if the IO...

Page 149: ...8 17 IDE Checklist Checklist Line Items Comments CBLID PDIAG cable detect Refer to the latest design guide for the correct circuit NOTE All ATA66 drives will have the capability to detect cables PDD 1...

Page 150: ...ies resistor 33 5 REF Series resistor 10 5 Table 8 19 FWH Flash BIOS Checklist Checklist Line Items Comments No floating inputs Unused FGPI pins need to be tied to a valid logic level INIT FWH Flash B...

Page 151: ...mended to be used for an onboard audio codec Only one primary codec can be present on the link A maximum of two active codecs are supported in an ICH platform The SDATAIN 0 1 pins should not be left i...

Page 152: ...Comments All voltage regulator components meet maximum current requirements Consider all loads on a regulator including other regulators All regulator components meet thermal requirements Ensure the...

Page 153: ...mine the optimal value This determination can include cost concerns commonality considerations manufacturing issues specifications and other considerations A simplistic DC calculation for a pullup val...

Page 154: ...Power Management Signals A power button is required by the ACPI specification PWRBTN is connected to the front panel on off power button The ICH integrates 16 msec debouncing logic on this pin AC powe...

Page 155: ...pen collector buffer pulled up to 2 5V using a 330 ohm resistor The circuitry checks for both processor VRM powered up and the PS_POK signal from the ATX power supply connector before asserting PWRGOO...

Page 156: ...ectly to soft off or a supported sleep state Poll the power button status bit during POST while SMIs are not loaded and go directly to soft off if it gets set Always install an SMI handler for the pow...

Page 157: ...9 Third Party...

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Page 159: ...1 Super I O Vendors Contact Phone SMC Dave Jenoff 909 244 4937 National Robert Reneau 408 721 2981 ITE Don Gardenhire 512 388 7880 Winbond James Chen 02 27190505 Taipei office Table 9 2 Clock Generat...

Page 160: ...7 AKM George Hill 408 436 8580 Cirrus Logic Crystal David Crowell 512 912 3587 Creative Technologies Ltd Ensoniq Corp Steve Erickson 408 428 6600 x6945 Diamond Multimedia Systems Theresa Leonard 360 6...

Page 161: ...thong chrontel com 408 544 2150 Conexant CN870 CN871 Eileen Carlson eileen carlson conexant com 858 713 3203 Focus FS450 FS451 Bill Schillhammer billhammer focusinfo com 978 661 0146 Philips SAA7102A...

Page 162: ...Third Party Vendor Information 9 4 Intel 810A3 Chipset Design Guide This page is intentionally left blank...

Page 163: ...A PCI Devices Functions Registers Interrupts...

Page 164: ...This page is intentionally left blank...

Page 165: ...97 Modem Controller Device 31 Function 7 Reserved 82810A3 GMCH Device 0 Function 0 Intel 82810A3 System and Memory Controller Device 1 Function 0 Intel 82810A3 Internal Graphics Device Table A 2 PCI D...

Page 166: ...A Intel 82801AA Bus Master IDE Controller Interrupt 14 IRQ14 Intel 82801AA USB Universal Host Controller Interrupt 18 PIRQC Intel 82801AA SMBus Controller Interrupt 17 PIRQB Reserved N A N A Intel 828...

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