Intel 810A3, Design Manual

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Intel
®
810A3 Chipset Design Guide vii
4-35 RAMDAC Component and Routing Guidelines ..........................................4-34
4-36 Recommended RAMDAC Reference Resistor Placement and
Connections ................................................................................................4-35
4-37 Recommended LC Filter Connection..........................................................4-36
4-38 Frequency Response (see Table 4-13 ).......................................................4-38
5-1 PICD[1,0] Uni-Processor Topology...............................................................5-7
5-2 Test Load vs. Actual System Load ...............................................................5-9
5-3 Aggressor and Victim Networks..................................................................5-11
5-4 Transmission Line Geometry: (A) Microstrip (B) Stripline ...........................5-11
5-5 One Signal Layer and One Reference Plane..............................................5-15
5-6 Layer Switch with One Reference Plane ....................................................5-15
5-7 Layer Switch with Multiple Reference Planes (same type) .........................5-15
5-8 Layer Switch with Multiple Reference Planes .............................................5-16
5-9 One Layer with Multiple Reference Planes.................................................5-16
5-10 Overdrive Region and V
REF
Guardband .....................................................5-19
5-11 Rising Edge Flight Time Measurement.......................................................5-19
6-1 Intel
®
810A3 Chipset Clock Architecture ......................................................6-2
6-2 Different Topologies for the Clock Routing Guidelines .................................6-5
6-3 Example of Capacitor Placement Near Clock Input Receiver.......................6-6
7-1 Intel
®
810A3 Chipset Power Delivery Architecture .......................................7-2
7-2 82810A3 GMCH Power Plane Decoupling ...................................................7-8
7-3 G3-S0 Transistion .........................................................................................7-9
7-4 S0-S3-S0 Transition....................................................................................7-10
7-5 S0-S5-S0 Transition....................................................................................7-11
8-1 Pullup Resistor Example.............................................................................8-15
8-2 PWRGOOD and PWROK Logic .................................................................8-17