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HP E1563A and E1564A Register-Based Programming
Appendix B
Figure B-1. Master Module Configuration.
TRIG:MODE
MASTer0 pairs TTLT0 (sample) with TTLT1 (trigger)
The MASTer0 module will function with all SLAVe0 modules.
1) The trigger source from the slave can be set
with the Trigger Source/Control Register bits
0,1,2,3,4,7,8,9,12,13,14, and 15.
.
2) SLAVe0 sets the TTLT0 line as if
the sample
source is TTLT0
and sets the TTLT1 line as if the
trigger source is
TTLT1
. These lines are simply
dedicated for synchronization between the
modules in the master-slave mode. You should
not use these lines for any other purpose.
MODE
Sample
signal
Trigger
signal
SLAVe0
TTLT0
TTLT1
SLAVe2
TTLT2
TTLT3
SLAVe4
TTLT4
TTLT5
SLAVe6
TTLT6
TTLT7
Summary of Contents for E1563A
Page 8: ......
Page 24: ...24 Digitizer Module Set up ...
Page 84: ...84 Digitizer Command Reference ...
Page 110: ...110 ...
Page 138: ...138 HP E1563A and E1564A Register Based Programming Appendix B ...
Page 156: ...156 HP E1563A and E1564A Verification Tests ...