HP E1563A, User Manual, Page: 119 / 166

HP E1563A and E1564A Register-Based Programming 119 Appendix B
Reading the Register
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Via Command Module PEEK command: DIAG:PEEK? 2083332,16
(2083328 = base with logical address 40 + 04 offset; see Figure B-2)
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Via Digitizer Module PEEK command: DIAG:PEEK? 2
(2 signifies the third word, 16 bits, zero-base numbering system)
A24 Offset Register
The offset of the module in A24 space is set by the upper eight bits (15-8) of
this register. The lower eight bits (7-0) of this register are zero.
A24 Offset register bits defined:
Cache FIFO High
Word Register
Data is stored on the module in large, slow dynamic RAM and fast, small
backplane cache. Each of these data stores is a FIFO. The dynamic RAM
FIFO receives the data from the ADC. As soon as the pre-trigger data has
been identified, data is moved from the dynamic RAM FIFO to the
backplane cache FIFO. Data is removed from the module using the cache
FIFO. Data is 16-bit 2’s compliment and is packed into the FIFO registers.
Always read register 08h before 0Ah if using D16. The FIFO is incremented
after reading register 0Eh. If D32 is used, reading 08h will increment the
FIFO correctly. The data is interwoven from all channels.
The following is the ordering of the data when D16 is used to remove the
data on a 4-channel module.
- Read 08h channel 1 data (bit 15 is MSB of chan1, bit 0 is LSB of chan 1)
- Read 0Ah channel 2 data
- FIFO is automatically incremented to bring in the next data
bit 12 A24 “1” sets A24 space as all FIFO, “0” sets A24 space as broken up.
bit 13 MOT-INTEL “1” = Motorola big endian byte swapping, “0” = Intel little endian byte swapping.
bit 14 M MODID bit; if the bit is "0", module has been selected.
bit 15 A A24/A32 enable; “1” = A32 decoding enabled, “0” = A24 decoding enabled.
**READ BITS (Status/Control Register)
base + 06
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write* A23 A22 A21 A20 A19 A18 A17 A16 undefined
Read** A24 Offset 0 0 0 0 0 0 0 0
*WRITE BITS (A24 Offset Register)
bits 8-15 A16-A23 These bits set the offset of the module in A24 space.
**READ BITS (A24 Offset Register)
bits 8-15 A24
Offset
The module’s offset in A24 space.