HP E1563A, User Manual, Page: 121 / 166

HP E1563A and E1564A Register-Based Programming 121 Appendix B
Interrupt Source
Register
Eight events can be enabled to interrupt the digitizer. These events are listed
in the above Interrupt Control Register definition for bits 8 through 15. The
Interrupt Source Register contains the latched version (bits 8-15) and the
unlatched version (bits 0-7) of these sources. The value of a source is
latched high when the source has a low-to-high transition. The latched bits
are cleared if they are masked as an interrupt source or by reading the
register and writing back the contents. Writing a “1” to the bit clears the
latch. The non-latched state of the interrupts is available all the time. The
bit ordering of the latched bits and the unlatched bits is the same as the mask.
Interrupt Source register bits defined:
**READ BITS (Interrupt Control Register)
bit 15 TRIG
A trigger has been received after pre-trigger acquisition is done.
bit 14 DONE
Memory is full or post trigger acquisition is done.
bit 13 PRE Pre-trigger data has been acquired.
bit 12 OVER
A dangerous OVERvoltage caused the channel input relay to open.
bit 11 CH4
Channel 4 exceeded the set limit.
bit 10 CH3 Channel 3 exceeded the set limit.
bit 9 CH2
Channel 2 exceeded the set limit.
bit 8 CH1
Channel 1 exceeded the set limit.
base + 0E
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read TRIG DONE PRE OVER CH4 CH3 CH2 CH1 TRIG DONE PRE OVER CH4 CH3 CH2 CH1
READ BITS (Interrupt Source Register)
bit 15, 7 TRIG A trigger has been received after pre-trigger acquisition is complete and
measurement count is not complete.
bit 14, 6 DONE Memory is full or post trigger acquisition is complete.
bit 13, 5 PRE Pre-trigger data has been acquired and waiting for trigger.
bit 12, 4 OVER A dangerous OVERvoltage caused the channel input relay to open.
bit 11, 3 CH4 Channel 4 exceeded the set limit during the last sample taken.
bit 10, 2 CH3 Channel 3 exceeded the set limit during the last sample taken.
bit 9, 1 CH2 Channel 2 exceeded the set limit during the last sample taken.
bit 8, 0 CH1 Channel 1 exceeded the set limit during the last sample taken.