HP 8924E, Assembly

Page: 476 / 640

476 C
hapter
11, B
lock D
iagra
m
s
A
ssem
bly Details
N:\m
kt\M
ANUAL
S\HP
8924C\AL
R
\blkd
ia.
fb
CDMA Data
HDBO-7
HRW
HSCC (CS1)
A6 PROTOCOL PROCESSOR
J65
10,11,12,13
14,15,16,17
18
C2,11-14
A1-8
A10
A11
A12
68EC020
Microprocessor
(25 Hz)
RESET 1
A13
First In First
Out (FIFO)
Interface
to the Host
Controller
GADDR
GDATA
G W/R
D_L_DataStruct
G_INTerupt
Data and
Address Buses
CODEC
(Encoder/
Decoder)
Interface
HSINT (CS1)
HCCE. (CS2)
HCCINT (CS2)
CODEC_ADR_0
CODEC_ADR_1
CODEC_ADR_2
J64
A13,14
B13,14,15
C13,14,15
C18
B17
B19
C17
C19
A16
B16
C16
Data To/From
the Cell Site
Digital
Assemblies
Address
Decode
Boot
ROM
FLASH
Memory
Flash Mem.
Controller
SRAM
Diagnostic LEDs
J64
C6
B31
20ms clock
PP2S (2 second clock)
Multi-
Function
Peripheral
Dual
Universal
Asynchronous
Receiver/
Transmitter
(DUART)
PROTO_DIAG_OUT
PROTO_DIAG_IN
PROTO_SER_OUT
PROTO_SER_IN
J65
B4
B5
B6
B7
To rear-panel
Diagnostic/
Protocol
Connector
J64
A7
B7
C12
C10
PROTO_TRIG1
PROTO_TRIG2
SYS_RESET (CS1)
SPC_RST (CS2)
To rear-panel
Cellsite/Triggers
Connector
To Cell Site
Digital
Assemblies
(J64) A9,11,15,17,19 - B20,23 - C9
(J65) B2,12,22,31
(J64) A32, B32, C32
(J65) B1, 13,32 - C32
(J65) B3
(J64)C31
(J64)A31
(A6-BD.FB)
Power Supplies and Ground:
Ground
+5V
+15V
+12.3V
+12.3V