Detector System Component Description
49
Built-In-Test Diagnostic Capability
All Synapse detectors incorporate built-in-test (BIT) circuitry that provides a
comprehensive level of testability to support the manufacturing process, as well as, field
maintainability. This BIT circuitry provides automated test capability via resident
diagnostic firmware routines to ensure the operational health of the detector and to
validate the detection system’s performance.
CCD Hardware Binning Control
Adding neighboring CCD pixels together to form a single pixel is a technique known as
binning. Binning can be accomplished in hardware during the readout process or through
software intervention (SynerJY) after the data has been collected from the CCD. This
binning process can be exercised at the hardware level in both the horizontal (x) and
vertical (y) directions for multiple areas of interest in a given readout as previously set-up
in the SynerJY software
.
Figure 14 on the following page illustrates a basic 2 x 2 binning operation on a 4 x 4
CCD array. This successful binning operation consists of two vertical clocking operations
followed by two horizontal clocking transfers that effectively shift the summed pixel
information into the output amplifier’s storage node prior to pixel readout and
digitization. This “super pixel,” once digitized, actually represents four pixels of the CCD
array.
It should be noted that binning does reduce resolution capability; however, it increases
sensitivity and improves (i.e. lowers) the overall CCD readout time. End-users are
cautioned that there is a limit to the effectiveness of hardware binning as a result of the
horizontal serial shift register and output node not having infinite capacity to store
charge. This physical limitation is best exemplified for applications that have a very
small signal superimposed on a large background. In practice, the pixels associated with
the horizontal register have twice the full well capacity of their light sensitive
counterparts, while the output node usually can hold four times that of the photosensitive
area. Thus, experiments where the summed charge exceeds either the full well capability
of the horizontal shift register and/or the output node will be lost from a data processing
point of view.
CCD Exposure Control
Synapse precisely controls CCD exposure time using a 1 kHz expose clock frequency
that provides flexible integration times of 0.001 to 4,294,967.296 sec (49.71 days). End-
users can set the desired exposure time with SynerJY application software.
Summary of Contents for JOBIN YVON SYNAPSE
Page 1: ...SYNAPSE CCD Detection System User Manual Part Number 81100 Revision 2...
Page 10: ...Preface x...
Page 14: ...System Description and Specifications 4...
Page 28: ...Detector System Installation 18...
Page 38: ...Initial Power up and Operation 28...
Page 48: ...Temperature Control 38...
Page 72: ...Appendix A Dimensional Drawings 62 Figure 17 Distance from Focal Plane to CCD Chip...
Page 73: ...Appendix A Dimensional Drawings 63 Figure 18 Synapse Power Supply Unit...
Page 74: ...Appendix A Dimensional Drawings 64...
Page 86: ...Appendix C Performing Routine Procedures with SynerJY 76...
Page 100: ...Appendix E Accessories 90...
Page 104: ...Warranty 94...
Page 113: ...103 Notes...
Page 114: ...104 Notes...