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4.11 Event Registers
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Standard Event Status Register (SESR) Bit Assignments
Bit 7
PON
Power on flag.
When the power is turned on, or on recovery from a power cut,
this bit is set to 1.
Bit 6
Unused.
Bit 5
CME
Command error.
When a command which has been received contains a syntactic or
semantic error, this bit is set to 1.
The command is not supported by the 3532-50/3522-50.
There is a mistake in a program header.
The number of data parameters is wrong.
The format of the parameters is wrong.
Bit 4
EXE
Execution error.
When for some reason a command which has been received
cannot be executed, this bit is set to 1.
The designated data value is outside the set range.
The designated data value is not acceptable.
Execution is impossible because some other function is being
performed.
Bit 3
DDE
Device dependent error.
When a command cannot be executed due to some cause other
than a command error, a query error, or an execution error, this
bit is set to 1.
Execution is impossible due to an abnormality inside the 3532-
50/3522-50.
During open or short circuit compensation, valid data cannot be
obtained.
Bit 2
QYE
Query error.
This bit is set to 1 when a query error is detected by the output
queue control.
When the data overflows the output queue.
When data in the output queue has been lost.
Bit 1
Unused.
Bit 0
Unused.
4.11 Event Registers
The 3532-50/3522-50 include three 8-bit event registers. It is possible to
determine the
status of the unit by reading these registers.
The event register is cleared in the following situations:
When a "
*
CLS" command is executed.
When an event register query is executed. (
*
ESR?, :ESR0?, :ESR1?)
When the unit is powered on.
(1) Standard event status register (SESR)
